module frame_sync(
	input clk,
	input rst_n,
	input FV1,
	input LV1,
	input [11:0] DIN1,
	input [11:0] DIN2,
	input FV2,
	input LV2,
	output reg FV,
	output reg LV,
	output reg [23:0] DOUT
  );

reg [1:0] q_fv_first;
reg q_fv_1,	q_fv_2, q_fv_1_1, q_fv_2_1,	q_lv_1,	q_lv_2, q_lv_1_1,	q_lv_2_1;
wire [11:0] w_first_data, w_dout;
reg [11:0] q_dout, q_dout_1, q_din1, q_din2, q_din1_1, q_din2_1;
wire w_wr_en, w_rd_en, w_fifo_rst; 

always@(posedge clk or negedge rst_n) begin
   if(!rst_n) begin
	q_fv_first	<=	0;
	q_fv_1		<=  0;
	q_fv_2		<=  0;
	q_fv_1_1	<=  0;
	q_fv_2_1	<=  0;
	q_lv_1		<=  0;
	q_lv_2		<=  0;
	q_lv_1_1	<=  0;
	q_lv_2_1	<=  0;
	FV			<=  0;
	LV			<=  0;
	DOUT		<=	0;
	q_dout		<=  0;
	q_dout_1	<=  0;
	q_din1		<=  0;
	q_din2		<=  0; 
   end
   else begin 
   	if ((q_fv_1==0&&q_fv_1_1==1) || (q_fv_2==0&&q_fv_2_1==1))
   		q_fv_first	<= 2'd0;
   	else if (q_fv_1==1&&q_fv_1_1==0&&q_fv_2==0)
   		q_fv_first	<= 2'd1;
   	else if (q_fv_2==1&&q_fv_2_1==0&&q_fv_1==0)
   		q_fv_first	<= 2'd2; 
   	else if (q_fv_1==1&&q_fv_1_1==0&&q_fv_2==1&&q_fv_2_1==0)
   		q_fv_first	<= 2'd3; 
   	else
   		q_fv_first	<= q_fv_first;
   	
   	
   	//q_fv_first	<=  ((FV1==0&&q_fv_1==1) || (FV2==0&&q_fv_2==1)) ? 2'd0 :	//first frame valid seen, 1=sensor1, 2=sensor2
   	//				(FV1==1&&q_fv_1==0&&FV2==0)      ? 2'd1 :
   	//				(FV2==1&&q_fv_2==0&&FV1==0)      ? 2'd2 :
	//				(FV1==1&&q_fv_1==0&&FV2==1&&q_fv_2==0) ? 2'd3 : 	  					
	//				q_fv_first;				
  	q_fv_1		<=  FV1;
  	q_fv_1_1	<=  q_fv_1;
  	q_fv_2		<=  FV2;
  	q_fv_2_1	<=  q_fv_2;
  	q_lv_1		<=  LV1;
  	q_lv_2		<=  LV2;
  	q_lv_1_1	<=  q_lv_1;
  	q_lv_2_1	<=  q_lv_2;
  	FV			<=  (q_fv_first==1)				? q_fv_2_1 :
	  				(q_fv_first==2)				? q_fv_1_1 :
	  				(q_fv_first==3)				? q_fv_1_1 :
  					(q_fv_first==0&&!q_fv_1_1&&!q_fv_2_1)	 ? 0 : FV;
  					
  	LV			<=  (q_fv_first==1)				? q_lv_2_1 :
	  				(q_fv_first==2)				? q_lv_1_1 :
	  				(q_fv_first==3)				? q_lv_1_1 :
  					(q_fv_first==0&&!q_lv_1_1&&!q_lv_2_1)	 ? 0 : LV;
  	q_dout		<= w_dout;
  	q_dout_1	<= q_dout;	 
	q_din1		<= DIN1;
	q_din1_1	<= q_din1;
	q_din2		<= DIN2;  
	q_din2_1	<= q_din2;
  	DOUT	<= (q_fv_first==1) ? {q_din2_1, w_dout} :
	  		   (q_fv_first==2) ? {w_dout, q_din1_1} :
	  		   (q_fv_first==3) ? {q_din2_1, q_din1_1}   : 0;	
  					
   end    
end

assign w_first_data = (q_fv_first==2'd1) ? q_din1 :		//data from first frame valid gets loaded into the fifo
					  (q_fv_first==2'd2) ? q_din2 : 0;

assign w_wr_en = (q_fv_first==2'd1 || q_fv_first==2'd2) ? 1 : 0;

assign w_fifo_rst = (~rst_n || (q_fv_first==2'd0)) ? 1 : 0;

assign w_rd_en = (q_fv_first==2'd1) ? q_fv_2_1 :
				 (q_fv_first==2'd2) ? q_fv_1_1 :	0;



FIFO_SYNC U1( 
                             .Reset(w_fifo_rst) 
                            ,.Clock(clk) 
                            ,.Din(w_first_data) 
                            ,.Write_enable(w_wr_en) 
                            ,.Read_enable(w_rd_en) 
                            ,.Dout(w_dout) 
                            ,.Full() 
                            ,.Empty() 
	                       ); 

endmodule