// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2010 by Lattice Semiconductor Corporation
// Permission:
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
// Disclaimer:
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.                
// --------------------------------------------------------------------                
//                     Lattice Semiconductor Corporation                
//                     5555 NE Moore Court                
//                     Hillsboro, OR 97214                
//                     U.S.A                         
//                     TEL: 1-800-Lattice (USA and Canada)                
//                          503-268-8001 (other locations)                
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// --------------------------------------------------------------------    
`timescale 1 ns / 1 ps
module deserializer
  #(
  parameter pmi_family = "XO2",
  parameter gearing    = "x4"
  )(
  input           eclk ,
  input           clk  ,
  input   [ 3:0]  dly  ,
  input           rstn ,
  input           din  ,
  output  [ 7:0]  dout 
  );

wire        ddel  	;

DELAYD delb_inst 
  (
  .A    (din      ), 
  .DEL0 (dly[0]   ), 
  .DEL1 (dly[1]   ), 
  .DEL2 (dly[2]   ),
  .DEL3 (dly[3]   ), 
  .DEL4	(1'b0	  ),
  .Z    (ddel     )
  );

generate                          
   if (pmi_family == "ECP3") begin
//*************************************************************************************
defparam ddr_inst.DR_CONFIG = "DISABLED" ;
IDDRX2D1 ddr_inst (
   .D      (ddel      ), 
   .SCLK   (clk       ), 
   .ECLK   (eclk      ),
   .QA0    (dout[0]   ), 
   .QB0    (dout[1]   ), 
   .QA1    (dout[2]   ), 
   .QB1    (dout[3]   )
   )/* synthesis GSR="DISABLED" IDDRAPPS="ECLK_DYNAMIC" */;   
   assign  dout[7:4]  =  4'b0000;
//*************************************************************************************
   end
   else if (pmi_family == "XO2" & gearing == "x4") begin //if (pmi_family == "XO2") begin
//*************************************************************************************
IDDRX4B ddr_inst 
  (
  .D		(ddel   ), 
  .ECLK		(eclk	), 
  .SCLK		(clk    ), 
  .RST  	(~rstn  ), 
  .ALIGNWD	(1'b0   ),
  .Q0		(dout[0]), 
  .Q1		(dout[1]), 
  .Q2		(dout[2]), 
  .Q3		(dout[3]),
  .Q4		(dout[4]), 
  .Q5		(dout[5]), 
  .Q6		(dout[6]), 
  .Q7		(dout[7])
  )/* synthesis GSR="DISABLED" */; 
//*************************************************************************************
   end
   else begin //if (pmi_family == "XO2") begin
//*************************************************************************************
IDDRX2E ddr_inst 
  (
  .D		(ddel   ), 
  .ECLK		(eclk	), 
  .SCLK		(clk    ), 
  .RST  	(~rstn  ), 
  .ALIGNWD	(1'b0   ),
  .Q0		(dout[0]), 
  .Q1		(dout[1]), 
  .Q2		(dout[2]), 
  .Q3		(dout[3])
  )/* synthesis GSR="DISABLED" */; 
  assign  dout[7:4]  =  4'b0000;
//*************************************************************************************
   end
endgenerate

endmodule