// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2010 by Lattice Semiconductor Corporation
// Permission:
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
// Disclaimer:
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.                
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//  Description:       Top level module for hispi HDR receiver        
//     Follow the definition in "TN-09-215: HiSPi Protocol Specification for the MT9M023 and MT9M033"
//  c_HDR_MODE_0 => c_WORD_WIDTH==20; c_LANE_WIDTH==4; c_PER_LANE_WIDTH==10
//  c_HDR_MODE_1 => c_WORD_WIDTH==14; c_LANE_WIDTH==3; c_PER_LANE_WIDTH==10
//  c_HDR_MODE_2 => c_WORD_WIDTH==12; c_LANE_WIDTH==3; c_PER_LANE_WIDTH==10
//  c_HDR_MODE_3 => c_WORD_WIDTH==14; c_LANE_WIDTH==2; c_PER_LANE_WIDTH==14
//  c_HDR_MODE_4 => c_WORD_WIDTH==12; c_LANE_WIDTH==2; c_PER_LANE_WIDTH==12
// --------------------------------------------------------------------  

module hispi_hdr_rx_core #(
parameter pmi_family     = "ECP3",
parameter c_WORD_WIDTH   = 20,
parameter c_LANE_WIDTH   = 4
)(
input clk_div2,
input rstn,
input [4*c_LANE_WIDTH-1:0] data_lane,

input flr_enable,
input start,
input pixel_clk,

output [c_WORD_WIDTH-1:0] dout    ,
output                    f_valid , 
output                    l_valid ,
output                    embeded_dvalid,
output [7:0]              embeded_data,
output test_out
);

endmodule