module hispi_wrap #(
parameter pmi_family    = "XO2"           , //"ECP3" or "XP2 or XO2"
parameter gearing       = "x4"            , //"x2" or "x4"
parameter c_HDR_MODE    = "false"	      , //"true" or "false"
parameter c_HISPI_MODE  = "Packetized-SP" , //"Packetized-SP" or "Streaming-SP" or "Streaming-S" or "ActiveStart-SP8"
parameter c_WORD_WIDTH  = 12              , //8/10/12/14/16
parameter c_LANE_WIDTH  = 4               , //LANE NUMBER 1/2/3/4	
parameter c_BRIDGES		= 1					//Number of HISPi to parallel bridges 1/2
)
(
	input rstn, 								//bridge reset
//hispi input port   
	input sclk_1,								//hispi sensor clock 1
	input [3:0] sdata_1,				//hispi sensor data	1
	input sclk_2,								//reserved; tie to ground
	input [3:0] sdata_2,				//reserved; tie to ground

//output ports
	output pclk,								//pixel clock
	output pixel_clk_x2,				//reserved; leave as 'open'
	output pixel_clk_x2_45deg,  //reserved; leave as 'open'
	output f_valid,							//frame valid
	output f_valid_2,						//reserved; leave as 'open'
	output l_valid,							//line valid
	output l_valid_2,						//reserved; leave as 'open'
	output [15:0] dout, 				//pixel data out
	output [15:0] dout_2,				//reserved; leave as 'open'
	output eb_dvalid,						//reserved; leave as 'open'
	output [7:0] eb_data				//reserved; leave as 'open'
	)/* synthesis syn_black_box */;
endmodule