/* Verilog module instantiation template generated by SCUBA Diamond_1.4_Production (87) */
/* Module Version: 5.2 */
/* Thu Dec 01 09:17:30 2011 */

/* parameterized module instance */
pll_ww12_4lane_xo2 __ (.CLKI( ), .RST( ), .CLKOP( ), .CLKOS( ), 
    .CLKOS2( ), .LOCK( ));
