// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2010 by Lattice Semiconductor Corporation
// Permission:
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
// Disclaimer:
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.                
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//                     Lattice Semiconductor Corporation                
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// --------------------------------------------------------------------                
//  Description:       Top level module for hispi receiver        
// --------------------------------------------------------------------  

`timescale 1 ns / 1 ps
module hispi_rx_top #(
parameter pmi_family     = "XO2", 			//"ECP3" or "XP2 or XO2"
parameter gearing        = "x4", 			//"x2" or "x4"
parameter c_HDR_MODE     = "false",         //"true" or "false"
parameter c_HISPI_MODE   = "Packetized-SP", //"Packetized-SP" or "Streaming-SP" or "Streaming-S" or "ActiveStart-SP8"
parameter c_WORD_WIDTH   = 12,              //10/12/14/16/20
parameter c_LANE_WIDTH   = 2                //LANE NUMBER 1/2/3/4             
)
(
input   rstn,
//hispi input port                        
input   sclk,                   
input   [c_LANE_WIDTH-1:0] sdata,	
//general configuration
input   flr_enable,     //1 indicates FLR is inserted
input   [13-1:0] pix_per_ln, //active pixels number per line, non used for "Packetized-SP" mode

//output port
input   pclk,
output  f_valid,	
output  l_valid,
output  [c_WORD_WIDTH-1:0] dout,
output  eb_dvalid,	
output  [7:0] eb_data,	

//optional monitor ports
input   start,   
output  clk_div4
	);
	
wire  [3:0] dly;
wire  [8*c_LANE_WIDTH-1:0]  data_lane;
wire  sclk_s;

//*******************************************************************************************************************************
assign dly = 4'b0110;
ECLKSYNCA ECLKSYNC (.ECLKI(sclk), .STOP(1'b0), .ECLKO(sclk_s));
CLKDIVC  #(.DIV ("4.0")) I_CLKDIVC( .CLKI (sclk_s), .RST (1'b0), .ALIGNWD (1'b0), .CDIV1 (), .CDIVX(clk_div4));
//*******************************************************************************************************************************
//ddrx4 __ (.alignwd(0), .clk(sclk), .clk_s(0), .init(0), .reset(0), .rx_ready( ), .sclk(clk_div4), .datain(sdata[3:0]), .q(data_lane[31:0]));

generate
genvar  gen_i;
  for (gen_i = 0 ; gen_i < c_LANE_WIDTH; gen_i = gen_i + 1 )
  begin : u_lane_deser

deserializer  #(
.pmi_family (pmi_family),
.gearing    (gearing)
) I_deserializer
  (
  .eclk (sclk_s          ),
  .clk  (clk_div4        ),
  .dly  (dly             ),
  .rstn (rstn            ),
  .din  (sdata[gen_i]     ),
  .dout (data_lane[8*(gen_i+1)-1:8*gen_i])
  );

  end // block: u_lane_deser
endgenerate

//*******************************************************************************************************************************


generate                          
   if (c_HDR_MODE == "true") begin
//*************************************************************************************
hispi_hdr_rx_core  #(
.pmi_family     (pmi_family     ),
.c_WORD_WIDTH   (c_WORD_WIDTH   ),
.c_LANE_WIDTH   (c_LANE_WIDTH   )
)
I_hispi_rx_core(
.clk_div2        (clk_div4        ),
.rstn            (rstn            ),
.data_lane       (data_lane       ),

.flr_enable      (flr_enable      ),
.start           (start           ),
.pixel_clk       (pclk            ),

.dout            (dout            ),
.f_valid         (f_valid         ), 
.l_valid         (l_valid         ),
.embeded_dvalid  (eb_dvalid       ),
.embeded_data    (eb_data         ),
.test_out        (                )
);
//*************************************************************************************
   end
   else if (c_HDR_MODE == "false") begin
//*************************************************************************************

hispi_rx_core #(
.pmi_family        (pmi_family        ),
.c_HISPI_MODE      (c_HISPI_MODE      ),
.c_WORD_WIDTH      (c_WORD_WIDTH      ),
.c_LANE_WIDTH      (c_LANE_WIDTH      )
)
I_hispi_rx_core(
.rstn            (rstn            ),
.clk_div2        (clk_div4        ),
.data_lane       (data_lane       ),
//general configuration
.flr_enable      (flr_enable      ), //1 indicates FLR is inserted
.pix_per_ln      (pix_per_ln      ), //active pixels number per line, non used for "Packetized-SP" mode
.start           (start           ),
.pixel_clk       (pclk            ),
//output port
.f_valid         (f_valid         ),
.l_valid         (l_valid         ),
.embedded_dvalid (eb_dvalid       ),	
.dout            (dout            ),
.test_out        (                )
);
//*************************************************************************************
   end
endgenerate

endmodule