module hispi_wrap #(
parameter pmi_family    = "XO2"           , //"ECP3" or "XP2 or XO2"
parameter gearing       = "x4"            , //"x2" or "x4"
parameter c_HDR_MODE    = "false"	      , //"true" or "false"
parameter c_HISPI_MODE  = "Packetized-SP" , //"Packetized-SP" or "Streaming-SP" or "Streaming-S" or "ActiveStart-SP8"
parameter c_WORD_WIDTH  = 12              , //8/10/12/14/16
parameter c_LANE_WIDTH  = 2               , //LANE NUMBER 1/2/3/4	
parameter c_BRIDGES		= 1					//Number of HISPi to parallel bridges 1/2
)
(
	input rstn, 
//hispi input port   
	input sclk_1,
	input [3:0] sdata_1,
	input sclk_2,
	input [3:0] sdata_2,

//output ports
	output pclk,
	output pixel_clk_x2,
	output pixel_clk_x2_45deg,
	output f_valid,	
	output f_valid_2,
	output l_valid,	
	output l_valid_2,
	output [15:0] dout, 
	output [15:0] dout_2,
	output eb_dvalid,
	output [7:0] eb_data
	);
wire clk_div4, pclk;
reg q_fv_dly, q_lv_dly, q_fv_dly_1, q_lv_dly_1;
reg [15:0] q_dout_dly, q_dout_dly_1;
wire n_f_valid, n_l_valid;
wire [15:0] n_dout;

/*always @(posedge pclk or negedge rstn)		
		if (~rstn) begin
			dout <= 0;
			f_valid <= 0;
			l_valid <= 0; 
			q_fv_dly <=0;
			q_lv_dly <=0;
			q_dout_dly<=0;			
			q_fv_dly_1 <=0;
			q_lv_dly_1 <=0;
			q_dout_dly_1<=0;
		end
		else begin
			q_dout_dly <= n_dout;
			q_fv_dly   <= n_f_valid;
			q_lv_dly   <= n_l_valid;   
			q_dout_dly_1 <= q_dout_dly;
			q_fv_dly_1   <= q_fv_dly;
			q_lv_dly_1   <= q_lv_dly;
			dout 	<= q_dout_dly_1;
			f_valid <= q_fv_dly_1;
			l_valid <= q_lv_dly_1;
			
		end	*/
pix_clock_gen #(
.pmi_family     (pmi_family		),
.c_WORD_WIDTH   (c_WORD_WIDTH	),
.c_LANE_WIDTH   (c_LANE_WIDTH  	) 
)
I_pix_clock_gen(
.rstn          (rstn          ),
.clk_div2      (clk_div4      ),
.pixel_clk     (pclk          ),
.pixel_clk_x2  (pixel_clk_x2  ),
.pixel_clk_x2_45deg(pixel_clk_x2_45deg),
.lock_status   (start         )
);

generate
	if(c_BRIDGES>0) begin
		hispi_rx_top #(
		.pmi_family     (pmi_family         ), //"ECP3" or "XP2 or XO2"
		.gearing        (gearing            ), //"x2" or "x4"
		.c_HDR_MODE     (c_HDR_MODE        	), //"true" or "false"
		.c_HISPI_MODE   (c_HISPI_MODE   	), //"Packetized-SP" or "Streaming-SP" or "Streaming-S" or "ActiveStart-SP8"
		.c_WORD_WIDTH   (c_WORD_WIDTH       ), //8/10/12/14/16
		.c_LANE_WIDTH   (c_LANE_WIDTH       )  //LANE NUMBER 1/2/3/4
		)
		I_hispi_rx_top(
			.rstn             (rstn),  //   
		//hispi input port   
			.sclk	          (sclk_1),
			.sdata            (sdata_1),
		//general configuration	
		.flr_enable       (1'b0          ), //1 indicates FLR is inserted
		.pix_per_ln       ('d1920        ), //active pixels number per line, non used for "Packetized-SP" mode

		//output ports
		.pclk           (pclk),
		.f_valid        (f_valid),	
		.l_valid        (l_valid),	
		.dout           (dout),
		.eb_dvalid	    (eb_dvalid ),
		.eb_data		(eb_data ),	

		//optional monitor ports
		.start            (start),
		.clk_div4         (clk_div4)
		);
	end
	if(c_BRIDGES>1) begin
		hispi_rx_top #(
		.pmi_family     (pmi_family         ), //"ECP3" or "XP2 or XO2"
		.gearing        (gearing            ), //"x2" or "x4"
		.c_HDR_MODE     (c_HDR_MODE        	), //"true" or "false"
		.c_HISPI_MODE   (c_HISPI_MODE   	), //"Packetized-SP" or "Streaming-SP" or "Streaming-S" or "ActiveStart-SP8"
		.c_WORD_WIDTH   (c_WORD_WIDTH       ), //8/10/12/14/16
		.c_LANE_WIDTH   (c_LANE_WIDTH       )  //LANE NUMBER 1/2/3/4
		)
		I_hispi_rx_top_1(
		.rstn         (rstn         ),     
		//hispi input port   
		.sclk	        (sclk_2     ),
		.sdata        (sdata_2    ),
		//general configuration	
		.flr_enable       (1'b0          ), //1 indicates FLR is inserted
		.pix_per_ln       ('d1920        ), //active pixels number per line, non used for "Packetized-SP" mode

		//output ports
		.pclk           (pclk    ),
		.f_valid        (f_valid_2),	
		.l_valid        (l_valid_2),	
		.dout           (dout_2   ),
		.eb_dvalid	    (eb_dvalid_2 ),
		.eb_data		(eb_data_2 ),	

		//optional monitor ports
		.start            (start),
		.clk_div4         ()
		);
	end
endgenerate 
endmodule