/* Verilog module instantiation template generated by SCUBA Diamond_1.3_Production (92) */
/* Module Version: 5.2 */
/* Sat Sep 24 20:16:24 2011 */

/* parameterized module instance */
pll_ww12_1lane_xo2 __ (.CLKI( ), .RST( ), .CLKOP( ), .LOCK( ));
