/* Verilog module instantiation template generated by SCUBA Diamond_1.4_Production (73) */
/* Module Version: 5.4 */
/* Fri Nov 11 13:31:58 2011 */

/* parameterized module instance */
FIFO_IN __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), 
    .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ), .AlmostEmpty( ), 
    .AlmostFull( ));
