/* Verilog netlist generated by SCUBA Diamond_1.3_Production (92) */
/* Module Version: 5.2 */
/* C:\lscc\diamond\1.3\ispfpga\bin\nt\scuba.exe -w -n IDDRRX2_XO2 -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type iol -mode in -io_type LVDS25 -width 1 -freq_in 100 -gear 2 -clk eclk -del 32 -e  */
/* Fri Sep 23 14:31:32 2011 */


`timescale 1 ns / 1 ps
module IDDRRX2_XO2 (alignwd, clk, clk_s, init, reset, rx_ready, sclk, 
    datain, q)/* synthesis syn_noprune=1 */;// exemplar attribute IDDRRX2_XO2 dont_touch true 
    input wire alignwd;
    input wire clk;
    input wire clk_s;
    input wire init;
    input wire reset;
    input wire [0:0] datain;
    output wire rx_ready;
    output wire sclk;
    output wire [3:0] q;

    wire scuba_vlo;
    wire opensync_0;
    wire opensync_1;
    wire opensync_cken;
    wire opensync_2;
    wire q3_0;
    wire q2_0;
    wire q1_0;
    wire q0_0;
    wire sclk_t;
    wire cdiv1;
    wire eclko;
    wire xstop;
    wire xstart;
    wire opensync_3;
    wire eclki;
    wire lock_chk;
    wire scuba_vhi;
    wire dataini_t0;
    wire buf_clk;
    wire buf_dataini0;

    defparam LUT4_1.initval =  16'h0a78 ;
    ROM16X1A LUT4_1 (.AD3(opensync_0), .AD2(opensync_3), .AD1(lock_chk), 
        .AD0(init), .DO0(opensync_cken));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam LUT4_0.initval =  16'hfffe ;
    ROM16X1A LUT4_0 (.AD3(opensync_0), .AD2(opensync_1), .AD1(scuba_vlo), 
        .AD0(scuba_vlo), .DO0(xstop));

    FD1P3BX FF_3 (.D(opensync_3), .SP(opensync_cken), .CK(clk_s), .PD(reset), 
        .Q(opensync_0))
             /* synthesis GSR="ENABLED" */;

    FD1P3DX FF_2 (.D(opensync_0), .SP(opensync_cken), .CK(clk_s), .CD(reset), 
        .Q(opensync_1))
             /* synthesis GSR="ENABLED" */;

    FD1P3DX FF_1 (.D(opensync_1), .SP(opensync_cken), .CK(clk_s), .CD(reset), 
        .Q(opensync_2))
             /* synthesis GSR="ENABLED" */;

    FD1P3DX FF_0 (.D(opensync_2), .SP(opensync_cken), .CK(clk_s), .CD(reset), 
        .Q(opensync_3))
             /* synthesis GSR="ENABLED" */;

    IDDRX2E Inst4_IDDRX2E0 (.D(dataini_t0), .ECLK(eclko), .SCLK(sclk_t), 
        .RST(reset), .ALIGNWD(alignwd), .Q0(q0_0), .Q1(q1_0), .Q2(q2_0), 
        .Q3(q3_0));

    defparam Inst3_CLKDIVC.DIV = "2.0" ;
    CLKDIVC Inst3_CLKDIVC (.RST(reset), .CLKI(eclko), .ALIGNWD(alignwd), 
        .CDIV1(cdiv1), .CDIVX(sclk_t));

    ECLKSYNCA Inst2_ECLKSYNCA (.ECLKI(eclki), .STOP(xstop), .ECLKO(eclko));

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    defparam udel_dataini0.DEL_VALUE = "DELAY0" ;
    defparam udel_dataini0.DEL_MODE = "ECLK_CENTERED" ;
    DELAYE udel_dataini0 (.A(buf_dataini0), .Z(dataini_t0));

    IB Inst1_IB0 (.I(datain[0]), .O(buf_dataini0))
             /* synthesis IO_TYPE="LVDS25" */;

    assign sclk = sclk_t;
    assign q[3] = q3_0;
    assign q[2] = q2_0;
    assign q[1] = q1_0;
    assign q[0] = q0_0;
    assign rx_ready = xstart;
    assign xstart = opensync_3;
    assign eclki = buf_clk;
    assign lock_chk = scuba_vhi;
    assign buf_clk = clk;


    // exemplar begin
    // exemplar attribute FF_3 GSR ENABLED
    // exemplar attribute FF_2 GSR ENABLED
    // exemplar attribute FF_1 GSR ENABLED
    // exemplar attribute FF_0 GSR ENABLED
    // exemplar attribute Inst1_IB0 IO_TYPE LVDS25
    // exemplar end

endmodule
