/* Verilog module instantiation template generated by SCUBA Diamond_1.3_Production (92) */
/* Module Version: 5.2 */
/* Sun Oct 30 10:29:10 2011 */

/* parameterized module instance */
pll_ww16_2lane_xo2 __ (.CLKI( ), .RST( ), .CLKOP( ), .LOCK( ));
