/* Verilog module instantiation template generated by SCUBA Diamond_1.3_Production (92) */
/* Module Version: 5.2 */
/* Fri Sep 23 14:31:32 2011 */

/* parameterized module instance */
IDDRRX2_XO2 __ (.alignwd( ), .clk( ), .clk_s( ), .init( ), .reset( ), 
    .rx_ready( ), .sclk( ), .datain( ), .q( ));
