// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2010 by Lattice Semiconductor Corporation
// Permission:
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
// Disclaimer:
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
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//   consistency and functionality through the use of formal
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//   regarding the use or functionality of this code.                
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//  Description:       
// --------------------------------------------------------------------  

`timescale 1 ns / 1 ps
module hispi_rx_core #(
parameter pmi_family     = "XO2",          //"ECP3" or "XP2"
parameter c_HISPI_MODE   = "Packetized-SP", //"Packetized-SP" or "Streaming-SP" or "Streaming-S" or "ActiveStart-SP8"
parameter c_WORD_WIDTH   = 12,              //10/12/14/16
parameter c_LANE_WIDTH   = 2                //LANE NUMBER 1/2/3/4
)
(
input    rstn,
input    clk_div2,
input   [8*c_LANE_WIDTH-1:0] data_lane,
//general configuration
input   flr_enable,     //1 indicates FLR is inserted
input   [13-1:0] pix_per_ln, //active pixels number per line, non used for "Packetized-SP" mode
input   start,
input   pixel_clk,
//output port
output  f_valid,	
output  l_valid,	
output  embedded_dvalid,	
output  [c_WORD_WIDTH-1:0] dout,
output  test_out
);


endmodule