// RAM Model
//
// +-----------------------------+
// |    Copyright 1996 DOULOS    |
// |       Library: Memory       |
// |   designer : John Aynsley   |
// +-----------------------------+

module RamChip (Address, Data, CLK, CS, WE);

parameter AddressSize = 14;
parameter WordSize = 16;

input [AddressSize-1:0] Address;
inout [WordSize-1:0] Data;
input CS, WE, CLK;

reg [WordSize-1:0] Mem [0:1<<AddressSize]; 
reg [WordSize-1:0] q_data_4, q_data_3, q_data_2,q_data_1,q_data;

initial begin
  $readmemh("Mem.mem",Mem);
end

assign Data = (!CS && WE) ?  q_data_2 : {WordSize{1'bz}};

always @(posedge CLK/*CS or WE*/) begin
  if (!CS && !WE)
    Mem[Address] <= Data;
  q_data	<= Mem[Address];
  q_data_1	<= q_data; 
  q_data_2	<= q_data_1;
  q_data_3	<= q_data_2;   //to represent cas=3	
  q_data_4	<= q_data_3;
end

endmodule