What is the SERDES channel to channel transmit skew for the LatticeSC?SupportArticlePage72c78446-7ba9-4c90-9162-8dd7d622d588FAQ/Support/AnswerDatabase/9/8/985https://edge.sitecorecloud.io/latticesemi9e32-latticesemi06bb-prod9ecc-d341/media/Project/Lattice/LatticeSemi/Images/SearchThumbnails/FAQ.png?sc_lang=enThe LatticeSC SERDES has a channel to channel transmit skew of only 200ps across all channels in the device. This tight transmit skew allows the LatticeSC device to be used in a number of parallel SERDES based applications such as PCI Express and SFI-5. There are two important requirements to achieve this level of skew control. The FPGA sourced refclk must be used for the SERDES reference clock. A low skew transmit reset must be implemented. The details for each of these requirements can be found in the LatticeSC/M flexiPCS/SERDES Design Guide ( TN1145.pdf )
