LatticeECP2M SMPTE SDI Evaluation Board

The LatticeECP2M SMPTE SDI Evaluation Board utilizes high-speed SERDES interfaces to demonstrate SMPTE 259 and 292 capabilities. This board, along with associated peripheral cables, demonstration programs and IP cores, is a complete solution designed to demonstrate the integration of HD-SDI, SDI and DVB-ASI encoders and decoders into an FPGA. The board can also be used to aid in the development of custom designs for the LatticeECP2M FPGA.

Device Support

You will need the following software to use this board:

  • ispLEVER for design, fitting, place & route of Lattice programmable devices
  • ispVM to download your program to the LatticeECP2M or on-board Flash memory devices
  • ORCAstra for on-chip FPGA register configuration.

LatticeECP2M SMPTE IP Solutions

The Multi-Rate Serial Digital Interface (SDI) PHY Layer IP core is a complete SDI PHY interface that connects to the high-speed SDI serial data on one side and formatted parallel data on the other side. It supports SMPTE standards 125M, 259M, 260M, 267M, 274M, 292M, 295M, and 296M and comprises high-speed serial I/Os (serializer/de-serializer or SerDes), SDI encoder, decoder, word alignment logic, CRC detection and checking logic, and rate detection logic. It is optimized to work with the LatticeECP2M/S embedded Physical Coding Sublayer (PCS) and SerDes, enabling a complete, single-chip solution ideally suited for a wide set of applications requiring high-performance, high-integration, and low-cost.

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Kit Contents

  • LatticeECP2M SMPTE SDI Evaluation Board featuring:
    • LFE2M35E-6F672C FPGA Device
    • Video interface for interconnection to video standard equipment
    • SATA interfaces to SERDES channels
    • PCI Express (x1) edge connector
    • MDR cable connections to demonstration of LVDS I/O signal integrity performance for rates up to 1Gbps
    • On-board Boot Flash; both Serial SPI Flash and Parallel Flash via MachXO™ programming bridge
    • On-board DDR2 memory components
    • SMAs for external high-speed clock / PLL inputs or data interfacing.
    • On-board and external reference clock sources
    • Various high-speed layout structures
    • LCD display via RS-232 and cable
    • Various LEDs, switches, connectors, I/O headers, high-speed layout structures, and on-board power control
  • ispDOWNLOAD cable for device programming
  • Power Supply
  • BNC and BNC->SMA video cables, and 75-Ohm BNC terminators

Board Photos

Top View

Click image to enlarge

Ordering Information

  • Reference number: LFE2M35E-V-EV
  • This board is available for short-term loans and demonstrations only.
  • Contact your local Lattice sales representative for further details.


Quick Reference
Technical Resources
LatticeECP2M SMPTE SDI Evaluation Board User's Guide
Describes the features and functionality of the LatticeECP2M SMPTE SDI Evaluation Board. Includes schematics.
EB27 01.4 12/17/2007 PDF 2.8 MB
Lattice SMPTE SDI Demo User's Guide
Explains how to use the SMPTE SDI Demo - available for download separately, along with the LatticeECP2M SMPTE SDI Evaluation Board and the Multi-Rate Serial Digital Interface (SDI) PHY Layer IP core.
UG02 01.1 7/11/2008 PDF 1.4 MB
LatticeECP3, LatticeECP2/M, LatticeXP2 7:1 LVDS Video Interface Reference Design Files
Contains Verilog and VHDL source files for RD1030 and use with the 7:1 LVDS Video Demo hardware from Lattice.
RD1030 1.5 4/12/2011 ZIP 1.8 MB
Lattice SMPTE SDI Demo Code
This contains all the design files and standard, configured IP block for use with the LatticeECP2M SMPTE SDI Evaluation Board and the Multi-Rate Serial Digital Interface (SDI) PHY Layer IP core. See the User's Guide (available for download separately)
1.1 7/11/2008 ZIP 777.1 KB
XO Parallel Flash Loader files
Used for ECP2M PCIe dev kit and SMPTE SDI board
5/22/2013 ZIP 628.7 KB

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