PAC-Designer Design Software

Powerful productivity – Design Tools for Power and Clock Management

Related Products

A perfect fit – PAC-Designer is custom tailored for designing with Power Manager and Platform Manager devices.

Get going, get done – PAC-Designer is the complete implementation and verification solution for Power Manager and Platform Manager devices.

Works well with others – Works seamlessly with Lattice Diamond software to let you easily develop innovative mixed signal solutions.

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Overview

Lattice sets the industry standard for integrated power, platform and clock management devices, and PAC-Designer design software is the key that unlocks the potential of these solutions for your design.

Move to a More Productive Environment

  • Fully integrated design and simulation environment for Platform Manager, Power Manager II, and ispClock devices
  • High level logic design mechanism
  • Easy-to-use GUI
  • For Platform Manager, PAC-Designer works in conjunction with ispLEVER to form a complete CPLD/FPGA design environment

Trust, but Verify

  • Export VHDL or Verilog HDL models to popular 3rd party HDL simulators
  • Create your power management stimulus graphically
  • Digital waveform simulation for easy design verification
  • Simulate power supply rate

Painless Programming

  • Use Diamond Programmer (included in Lattice Diamond) to download your designs to silicon for Platform Manager
  • For products other than Platform Manager, PAC-Designer can be used directly to program Platform Manager, Power Manager II and ispClock devices

Licensing

PAC-Designer License (only required for PAC-Designer 5.1 or earlier)

To request a license you will need the following:

  • Lattice website user account
  • Hard drive serial number

Click here to request your license.

Software Downloads & Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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Fail-Safe Sequencing During Field Upgrades Source Files
DT6088 1.2 6/6/2012 ZIP 591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN6088 01.2 6/6/2012 PDF 1.1 MB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN6076 01.0 12/12/2007 PDF 215.9 KB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN6067 01.0 11/21/2005 PDF 563.7 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN6070 01.0 11/21/2005 PDF 540.1 KB
Using ispVM System to Program ispPAC Devices
AN6062 01.0 5/1/2004 PDF 709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN6054 01.0 11/23/2005 PDF 276.3 KB
Powering Up and Programming the ispPAC-POWR607
AN6078 01.1 4/21/2011 PDF 1.3 MB
Scalable Centralized Power Management Source Files
DT6089 1.2 6/6/2012 ZIP 520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN6089 01.2 6/6/2012 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Fail-Safe Sequencing During Field Upgrades Source Files
DT6088 1.2 6/6/2012 ZIP 591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN6088 01.2 6/6/2012 PDF 1.1 MB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN6076 01.0 12/12/2007 PDF 215.9 KB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN6067 01.0 11/21/2005 PDF 563.7 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN6070 01.0 11/21/2005 PDF 540.1 KB
Using ispVM System to Program ispPAC Devices
AN6062 01.0 5/1/2004 PDF 709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN6054 01.0 11/23/2005 PDF 276.3 KB
Powering Up and Programming the ispPAC-POWR607
AN6078 01.1 4/21/2011 PDF 1.3 MB
Scalable Centralized Power Management Source Files
DT6089 1.2 6/6/2012 ZIP 520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN6089 01.2 6/6/2012 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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PAC-Designer Installation Notice 6.32
6.32 2/22/2016 PDF 387.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Platform Management Utility Functions IP Core User's Guide
IPUG94 01.1 1/24/2011 PDF 551.8 KB
Power Manager II Hercules Development Kit User's Guide
EB57 01.0 12/22/2010 PDF 3 MB
Platform Manager Development Kit User's Guide
EB58 01.2 12/7/2010 PDF 1.6 MB
Platform Designer 3.11 User Guide
1.0 6/1/2019 PDF 697.9 KB
PAC-Designer Software User Manual 6.32
1.0 6/1/2014 PDF 3.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Serial Peripheral Interface (SPI) - Documentation
RD1075 1.1 12/23/2011 PDF 158.7 KB
SPI GPIO Expander - Documentation
RD1073 1.1 12/23/2010 PDF 212.5 KB
Temperature Monitor Using Platform Manager Documentation
RD1080 1.0 9/28/2010 PDF 330 KB
SPI GPIO Expander - Source Code
RD1073 1.1 12/23/2010 ZIP 161.6 KB
Serial Peripheral Interface (SPI) - Source Code
RD1075 1.1 12/23/2011 ZIP 124.8 KB
UART (Universal Asynchronous Receiver/Transmitter) - Documentation
RD1011 1.6 6/14/2011 PDF 346.3 KB
Temperature Monitor Using Platform Manager Source Files
RD1080 1.0 9/28/2010 ZIP 256.7 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
RD1011 1.7 1/1/2015 ZIP 766.4 KB
GPIO Expander, Documentation
RD1065 1.3 4/12/2011 PDF 280.6 KB
Error Logging Using Platform Manager Documentation
RD1077 1.0 9/28/2010 PDF 422.5 KB
GPIO Expander, Source Code
RD1065 1.3 4/12/2011 ZIP 195.5 KB
I2C Slave to SPI Master Bridge - Documentation
FPGA-RD-02111 1.2 1/29/2021 PDF 863.9 KB
Hercules Development Kit Demonstration Source Code
1.0 6/11/2010 ZIP 201.6 KB
Error Logging Using Platform Manager Source Files
RD1077 1.0 9/28/2010 ZIP 372.9 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD1005 5.9 1/10/2015 ZIP 809.7 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD1005 5.8 3/6/2014 PDF 987.4 KB
I2C Slave to SPI Master Bridge - Source Code
RD1094 1.1 12/23/2011 ZIP 180.4 KB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-02106 4.9 1/29/2021 PDF 918.1 KB
Closed Loop Power Supply Trimming Source Code
RD1078 1.0 12/6/2010 ZIP 269.4 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD1001 7.3 4/18/2011 ZIP 152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD1002 4.6 3/13/2014 ZIP 2.6 MB
Closed Loop Power Supply Trimming Documentation
RD1078 1.0 12/6/2010 PDF 278.2 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-02105 7.4 1/29/2021 PDF 993.7 KB
PWM Fan Controller - Source Code
RD1060 1.7 1/16/2015 ZIP 2.9 MB
Power Management Bus Reference Design Documentation
FPGA-RD-02097 1.2 1/22/2021 PDF 1.1 MB
Power Management Bus Reference Design - Source Code
RD1100 1.1 12/23/2011 ZIP 378.3 KB
Platform Manager Dev Kit Initial Demo Source Files
1.1 1/26/2011 ZIP 1.1 MB
PWM Fan Controller
RD1060 1.6 9/10/2014 PDF 481.5 KB
Long Delay Timers Using Platform Manager Documentation
RD1079 1.1 9/28/2010 PDF 874.1 KB
Long Delay Timers Using Platform Manager Source Files
RD1079 1.0 9/28/2010 ZIP 683.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Platform Manager Product Brochure
I0208 1.0 4/10/2012 PDF 2.8 MB
Platform Manager Product Brochure (Chinese)
I0208C 1.0 6/4/2012 PDF 2.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Software Cable Support
2.0 7/16/2012 PDF 194.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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PAC-Designer Tutorial: Designing Power Manager II
This tutorial shows you how to use several processes, tools, and reports of the PAC-Designer software suite to program digital and analog elements of the ispPAC®-POWR1220AT8 device. 		PDT01 01.1 8/15/2008 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Platform Manager 208 ftBGA BSDL Files
1.1 2/27/2014 ZIP 10 KB
LPTM10_1247_MO640
1.01 10/8/2014 BSM 24.9 KB
LPTM10_12107_XO640
1.01 10/8/2014 BSM 30.3 KB
Platform Manager 128 TQFP BSDL Files
1.1 2/26/2013 ZIP 8.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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PAC Designer 6.30 for Windows
6.32 9/26/2023 ZIP 120.1 MB
Selecting Power and Platform Manager Devices Excel Spreadsheet Tool
1.1 3/19/2012 ZIP 63.1 KB

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