[Blog] Lattice Mach-N2: Advancing Secure Control for Modern InfrastructureBlogEntryPage90c940e0-abb2-4244-97c3-78e3027b4b02Blog/Blog/2026/Lattice-Mach-N2-Advancing-Secure-Control-for-Modern-Infrastructurehttps://edge.sitecorecloud.io/latticesemi9e32-latticesemi06bb-prod9ecc-d341/media/Project/Lattice/LatticeSemi/Images/SearchThumbnails/blog.png?sc_lang=enIn this blog, we discuss the launch of the Lattice Mach-N2 family, a new generation of secure control FPGAs built on the Lattice Nexus 2 platform, offering the only full CNSA 2.0-compliant post-quantum cryptography suite in its class, with crypto-agile security, high-speed connectivity, and robust physical protections designed to future-proof modern data center and network infrastructure against evolving cryptographic threats.Cyberattacks on data center, network, and edge infrastructure are increasing in frequency and sophistication. NIST's post-quantum cryptography (PQC) standards are finalized, and the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) is now in effect. For systems with long lifecycles, the window to act is narrowing. Today, we introduced the Lattice Mach -N2 family, a new generation of secure control FPGAs delivering increased logic density, a full CNSA 2.0-compliant PQC suite, and the high-speed connectivity required for modern infrastructure. What Is Lattice Mach-N2? Built on the Lattice Nexus 2 platform , Mach-N2 expands on the capabilities of Lattice MachXO5 -NX FPGAs, adding greater logic density and performance, ranging from 65k to 220k System Logic Cells (SLC). Integrated on-chip flash enables instant-on boot, making Mach-N2 the first device powered up and the last powered down in any system. Mach-N2 adds PCIe 4.0 and 16G SERDES for high-speed, direct connection to modern processors. Security: CNSA 2.0-Compliant, Crypto-Agile Mach-N2 is the only control FPGA in its class that combines internal configuration flash, boots under 30ms, and supports a full CNSA 2.0-compliant PQC suite. Key security capabilities include: Full PQC algorithm suite: ML-DSA, LMS, and XMSS for authentication; ML-KEM for key exchange Crypto agility: field-updatable cryptographic algorithms with anti-rollback protection, enabling security posture to adapt as standards evolve PUF-derived unique device identity supporting DICE and SPDM attestation User-accessible cryptographic APIs for securing the broader platform AES-256-GCM, ECC521, and RSA4096 for backward compatibility with classical algorithms Physical Security and Reliable Recovery On-chip flash physically blocks external access to bitstream and user flash memory by design. Mach-N2 supports three configuration images -- primary, secondary, and golden (recovery). Voltage and temperature monitoring with user-configurable anti-tamper responses provide layered physical protection. High-Speed Connectivity Mach-N2 supports PCIe 4.0, 10G Ethernet, and 16G SERDES, providing the connectivity required to operate alongside modern high-performance processors in data center and network applications. Availability Lattice Mach-N2 is sampling today to major customers, with development kits and software support available via Lattice Radiant and Lattice Prompt . To explore Lattice Mach-N2 and what CNSA 2.0-compliant PQC means for your design, visit the Lattice Mach-N2 product page and download the white paper[SH2.1]. To bolster your system security and control architecture, contact our team today.Cyberattacks on data center, network, and edge infrastructure are increasing in frequency and sophistication. NIST's post-quantum cryptography (PQC) standards are finalized, and the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) is now in effect. For systems with long lifecycles, the window to act is narrowing. Today, we introduced the Lattice Mach -N2 family, a new generation of secure control FPGAs delivering increased logic density, a full CNSA 2.0-compliant PQC suite, and the high-speed connectivity required for modern infrastructure. What Is Lattice Mach-N2? Built on the Lattice Nexus 2 platform , Mach-N2 expands on the capabilities of Lattice MachXO5 -NX FPGAs, adding greater logic density and performance, ranging from 65k to 220k System Logic Cells (SLC). Integrated on-chip flash enables instant-on boot, making Mach-N2 the first device powered up and the last powered down in any system. Mach-N2 adds PCIe 4.0 and 16G SERDES for high-speed, direct connection to modern processors. Security: CNSA 2.0-Compliant, Crypto-Agile Mach-N2 is the only control FPGA in its class that combines internal configuration flash, boots under 30ms, and supports a full CNSA 2.0-compliant PQC suite. Key security capabilities include: Full PQC algorithm suite: ML-DSA, LMS, and XMSS for authentication; ML-KEM for key exchange Crypto agility: field-updatable cryptographic algorithms with anti-rollback protection, enabling security posture to adapt as standards evolve PUF-derived unique device identity supporting DICE and SPDM attestation User-accessible cryptographic APIs for securing the broader platform AES-256-GCM, ECC521, and RSA4096 for backward compatibility with classical algorithms Physical Security and Reliable Recovery On-chip flash physically blocks external access to bitstream and user flash memory by design. Mach-N2 supports three configuration images -- primary, secondary, and golden (recovery). Voltage and temperature monitoring with user-configurable anti-tamper responses provide layered physical protection. High-Speed Connectivity Mach-N2 supports PCIe 4.0, 10G Ethernet, and 16G SERDES, providing the connectivity required to operate alongside modern high-performance processors in data center and network applications. Availability Lattice Mach-N2 is sampling today to major customers, with development kits and software support available via Lattice Radiant and Lattice Prompt . To explore Lattice Mach-N2 and what CNSA 2.0-compliant PQC means for your design, visit the Lattice Mach-N2 product page . To bolster your system security and control architecture, contact our team today.FPGA, secure control FPGA, PQC, CNSA 2.0, ML-KEM, Nexus 2, crypto agility, secure boot, hardware Root of Trust2026-09-17T19:00:00Z
[Blog] Lattice Mach-N2: Advancing Secure Control for Modern Infrastructure
Posted 09/17/2026 by Lattice Semiconductor
Cyberattacks on data center, network, and edge infrastructure are increasing in frequency and sophistication. NIST's post-quantum cryptography (PQC) standards are finalized, and the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) is now in effect. For systems with long lifecycles, the window to act is narrowing.
Today, we introduced the Lattice Mach™-N2 family, a new generation of secure control FPGAs delivering increased logic density, a full CNSA 2.0-compliant PQC suite, and the high-speed connectivity required for modern infrastructure.
What Is Lattice Mach-N2?
Built on the Lattice Nexus™ 2 platform, Mach-N2 expands on the capabilities of Lattice MachXO5™-NX FPGAs, adding greater logic density and performance, ranging from 65k to 220k System Logic Cells (SLC). Integrated on-chip flash enables instant-on boot, making Mach-N2 the first device powered up and the last powered down in any system. Mach-N2 adds PCIe® 4.0 and 16G SERDES for high-speed, direct connection to modern processors.
Security: CNSA 2.0-Compliant, Crypto-Agile
Mach-N2 is the only control FPGA in its class that combines internal configuration flash, boots under 30ms, and supports a full CNSA 2.0-compliant PQC suite.
Key security capabilities include:
- Full PQC algorithm suite: ML-DSA, LMS, and XMSS for authentication; ML-KEM for key exchange
- Crypto agility: field-updatable cryptographic algorithms with anti-rollback protection, enabling security posture to adapt as standards evolve
- PUF-derived unique device identity supporting DICE and SPDM attestation
- User-accessible cryptographic APIs for securing the broader platform
- AES-256-GCM, ECC521, and RSA4096 for backward compatibility with classical algorithms
Physical Security and Reliable Recovery
On-chip flash physically blocks external access to bitstream and user flash memory by design. Mach-N2 supports three configuration images -- primary, secondary, and golden (recovery). Voltage and temperature monitoring with user-configurable anti-tamper responses provide layered physical protection.
High-Speed Connectivity
Mach-N2 supports PCIe 4.0, 10G Ethernet, and 16G SERDES, providing the connectivity required to operate alongside modern high-performance processors in data center and network applications.
Availability
Lattice Mach-N2 is sampling today to major customers, with development kits and software support available via Lattice Radiant® and Lattice Prompt™.
To explore Lattice Mach-N2 and what CNSA 2.0-compliant PQC means for your design, visit the Lattice Mach-N2 product page. To bolster your system security and control architecture, contact our team today.
