Watchdog Timer IP Core

Features a Two-Stage Timer Supporting Non-Maskable Interrupt and a Hard Reset

Related Products

Related Applications

​​The Watchdog Timer IP is designed for use as an indicator that corrective action is needed in response to a computer or processor malfunction. The design features a two-stage timer that supports non-maskable interrupt and a hard reset. It is a two-stage timer that starts to count depending on the status of the processor. ​

Features

  • Seamlessly work with sleep mode
  • Programmable timer spec 50-500 ms (10 ms)
  • Two-stage timer that supports warm boot and cold boot resets
  • You can specify in cycles or time
  • Supports trigger input, reset and NMI output

Jump to

Block Diagram

Watchdog Timer IP Core Block DiagramExpand Image

Resource Utilization

IP Configuration for Avant Family
LAV-AT-500E-3LFG1156I
Configuration Clk Fmax (MHz)1 Registers LUTs DSP
Default 245.58 51 77 0
Enable APB = Checked
Others = Default		 231.7 109 164 0
Timer Stage 1 Number of Cycles: 500,
Timer Stage 2 Number of Cycles: 500,
Others = Default		 251.76 37 57 0
Timer Stage 1 Number of Cycles: 75000000,
Timer Stage 2 Number of Cycles: 75000000,
Others = Default		 251.76 51 77 0
Mode: Time,
System Clock Frequency: 150,
Others = Default		 251.76 51 77 0
Mode: Time,
Timer Stage 1 Timeout: 500,
Timer Stage 2 Timeout: 500,
Others = Default		 251.76 52 77 0

1. Fmax is generated when the FPGA design only contains Watchdog Timer IP Core, and the target frequencies are 150 MHz (for configured System Clock Frequency) and 100MHz (for other configuration). These values may be reduced when user logic is added to the FPGA design.

IP Configuration for Nexus Family
LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)1 Registers LUTs DSP
Default 169.66 51 100 0
Enable APB = Checked
Others = Default		 200 109 181 0
Timer Stage 1 Number of Cycles: 500,
Timer Stage 2 Number of Cycles: 500,
Others = Default		 200 37 73 0
Timer Stage 1 Number of Cycles: 75000000,
Timer Stage 2 Number of Cycles: 75000000,
Others = Default		 200 51 98 0
Mode: Time,
System Clock Frequency: 150,
Others = Default		 200 51 106 0
Mode: Time,
Timer Stage 1 Timeout: 500,
Timer Stage 2 Timeout: 500,
Others = Default		 189.97 52 107 0

1. Fmax is generated when the FPGA design only contains Watchdog Timer IP Core, and the target frequencies are 150 MHz (for configured System Clock Frequency) and 100MHz (for other configuration). These values may be reduced when user logic is added to the FPGA design.

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)1 Registers LUTs DSP
Default 132.14 51 100 0
Enable APB = Checked
Others = Default		 152.02 109 181 0
Timer Stage 1 Number of Cycles: 500,
Timer Stage 2 Number of Cycles: 500,
Others = Default		 170.45 36 73 0
Timer Stage 1 Number of Cycles: 75000000,
Timer Stage 2 Number of Cycles: 75000000,
Others = Default		 143.74 51 98 0
Mode: Time,
System Clock Frequency: 150,
Others = Default		 172.56 51 107 0
Mode: Time,
Timer Stage 1 Timeout: 500,
Timer Stage 2 Timeout: 500,
Others = Default		 163.99 52 107 0

1. Fmax is generated when the FPGA design only contains Watchdog Timer IP Core, and the target frequencies are 150 MHz (for configured System Clock Frequency) and 100MHz (for other configuration). These values may be reduced when user logic is added to the FPGA design.

Resource Utilization
Configuration Clk Fmax (MHz) Slice Registers LUTs EBRs
Default 175.840MHz 52 116 0
Timer Stage 1 Timeout = 1050, Others = Default 200MHz 52 117 0
Mode Time, Clock Frequency = 150, Others = Default 189.107 52 128 0
Mode Time, Timer Stage 2 Timeout = 100, Others = Default 160.154MHz 2 126 0

Ordering Information

The Watchdog Timer IP Core is available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Information Resources
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Watchdog Timer IP Core - User Guide
FPGA-IPUG-020971.96/26/2026PDF1.4 MB

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Watchdog Timer IP Core - Release Notes
FPGA-RN-020241.06/26/2026PDF348.6 KB