The Lattice QSPI Flash Controller IP core supports the SPI, DSPI, and QSPI protocols to perform operations on the target flash device. A Quad Serial Peripheral Interface (QSPI) uses four tri-state data lines and is commonly used to program, erase, and read SPI flash memories. QSPI enhances the throughput of a standard SPI by four times since four bits are transferred with every clock cycle.
Resource Utilization details are available in the IP Core User Guide.
Features
- Different bus interfaces:
- AMBA 3 AHB-Lite Protocol v1.0
- AMBA AXI4-Lite Protocol (for CSR access only)
- AMBA AXI4 Protocol
- Scalable performance: 1X, 2X, 4X I/O widths.
- Programmable SPI clock mode of 0 or 3.
- Programmable serial clock frequency.
- Optional use of transmit and receive FIFOs with configurable FIFO depth for register-based access only.
