PC/Server Clock Management

Devices Used

• MachXO or XPLD

Functions Performed

• Dual PLL Clock generation - Glue Logic
• Pwr/Rst Control
• Hot Swap Control
• VRM/VID Control

Lattice Advantages

• One Chip for all Clock & logic needs
• Generate Clocks such as:
  • 4x CLK33 PCI
  • 2x CLK49 CTT33
  • 2x CLK66 PCI/SSTL3_I/SSTL3_I/AGP_1X/LVTTL
  • 8x CLK66 PCI-X
  • 6x CLK100 LVDS
  • 4x CLK100 SSTL3_I
  • 2x CLK133 GTLPLUS/LVPECL
  • 4x CLK133 PCI-X
  • 8x CLK SSTL3_I
• Optional Variable Phase Skew
• Zero Phase Delay Options
• Multiple Outputs with sysIO Standards
• Low Jitter 100 ps
• Programmable on the fly
• sysIO