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Optimized FPGA Architecture for Low Cost Non-Volatile Applications
The LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with Flash Non-volatile cells in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK embedded block memories and Serial TAG memory and design security. The parts also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 FPGA fabric utilizes an underlying LatticeECP2 architecture that was optimized from the outset with high performance and low cost in mind. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP blocks.
- Download the LatticeXP2 Family Handbook
- AEC-Q100 Qualified
- Operating Range: -40°C to +125°C TJ
- Single Chip Solution - Small footprint, instant-on and complete design security through on-chip Flash
- Low Cost Mainstream FPGA Architecture
- Densities from 5K to 17K lookup tables (LUTs)
- Fast, secure design changes - Live Update Programmability
- On-chip DSP Blocks - Three to five blocks for high performance multiply, accumulate
- Pre-Engineered DDR and LVDS I/O Interfaces - DDR / DDR2 interfaces up to 166 MHz
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