For many applications, more general purpose I/O (GPIO) ports are required than those available on a microprocessor. This design provides a solution that uses a Lattice PLD as a GPIO Expander. It provides additional control (control signal and data output signal) and monitoring (input data signal) capabilities when the microprocessor has insufficient I/O ports. The design interfaces a microprocessor with a back-end device through a common timing specification.
| Device Family | Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|---|
| MachXO™ | LCMXO640C-3T100C | Verilog/VHDL | >100 MHz | 47 | 238/206 LUTs | 1.2 |
| ispMACH® 4000ZE | LC4256ZE-5TN100C | Verilog/VHDL | >100 MHz | 47 | 187/194 Macrocells | 1.2 |
| LatticeECP3 | LFE3-17EA-6FTN256C | Verilog/VHDL | > 100 MHz | 47 | 242/211 LUTs | 1.3 |
| LatticeXP2™ | LFXP2-5E-5TN144C | Verilog/VHDL | >100 MHz | 47 | 277/274 LUTs | 1.3 |
| Platform Manager™ | LPTM10-12107-3FTG208CES | Verilog/VHDL | >100 MHz | 47 | 250/207 LUTs | 1.2 |
download design documentation (RD1065)
RD1065 GPIO Expander - Source Code
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
