XpressLite PCI Express x1 Controller for LatticeECP2M FPGAs

Download the datasheet

Overview

PCI Express is a third-generation, high-bandwidth, low-voltage, differential serial interconnect technology that maintains compatibility with existing PCI infrastructures.  It is designed to offer performance for today's I/O bandwidth needs while offering the I/O infrastructure upon which can be leveraged for future system development. 

PLDA's XpressLite PCI Express x1 Controller includes a complete PCI Express x1 IP core integrated with a scatter-gather DMA controller.  This provides a complete system solution for PCI Express-based systems with non-contiguous blocks of memory where high data throughput is required between a host system and a device.

The PLDA XpressLite core adheres to the Intel PHY Interface for PCI Express™ (PIPE) architecture standard, which provides an interface with different data widths, frequencies of operation, and status and error management methods.  A PHY interface module has been designed to seamlessly connect the XpressLite core logic and the LatticeECP2M PHY layer.  The core is delivered integrated with the PHY interface module, and is supported by a Lattice-specific XpressLite design kit and the LatticeECP2M PCI Express Evaluation Board.  It has been validated with the board, and performance is supported by mid-speed grade versions of the LatticeECP2M family, providing significant cost savings versus competing FPGA-based PCI Express solutions.

Typical PCI Express Fabric

Implementation Results

The following are typical performance and utilization results.

 ¹ Performance and utilization characteristics are generated using an LFE2M-35E-6F672C. When using this IP core in a different density, package, speed, or grade within the LatticeECP2M family, performance and utilization may vary. 

² Includes scatter-gather DMA logic.

Features

• x1 lane endpoint configuration'
• Supports 1 Virtual Channel (VC)
• 256 Byte maximum payload size
• Implements all 3 PCI Express layers (Transaction, Data Link, Physical)
• Implements all Configuration Space registers
• Supports 1, 2, 4, or 8 outstanding requests
• Supports multiple power management modes:  all power states, legacy PCI power management, native active state power management/L0 state
• Small core size provides low implementation cost  
• PCI Express™ Base Specification Revision 1.1 compliant

PCI Express Development Tools

Lattice and PLDA provide a combined development tool suite which enables a complete PCI Express system to be quickly prototyped.  Lattice provides the LatticeECP2M PCI Express Evaluation board, which is fitted with a LatticeECP2M-35 device.  The board can also be connected to a logic analyzer or another board/system using the cable headers.   The LatticeECP2M device incorporates a Physical Coding Sublayer (PCS), which implements the PHY layer on-chip, eliminating the need for an external PHY chip.

PLDA offers a robust set of PCI Express tools including a PCI manager, Configuration Manager, Memory Manager, DMA Demo, and c-source code files for all these tools.  A Reference Design, drivers, and API are also available.  When used with the LatticeECP2M PCI Express evaluation board, a complete prototype can be quickly developed which demonstrates the IP core and board's capabilities.  The PLDA Development Tools are available immediately. Contact your Lattice sales office for availability of the LatticeECP2M PCI Express Evaluation Board.