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IEEE 1588 Syn1588®Clock_S Core

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Download the datasheet

The SYN1588®Clock_S IP-core provides highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for Industrial Ethernet applications. It provides a high resolution, high accuracy hardware clock which uses a 96-bit wide adder based clock architecture allowing supporting input clock frequencies in the range of 10 – 200 MHz. Furthermore the SYN1588 Clock_S comprises an MII-Scanner unit, which scans all Ethernet traffic in search for IEEE 1588 synchronization packets. Upon detection of any such packet it draws a 96-bit wide time stamp from the local clock any copies it together with status and identification data into a time-stamp FIFO.

Block Diagram

This diagram shows the Syn1588 Clock_S IP Core highlighted in green and how it is connected into the communication system.

 Oregano IEEE 1588 Syn1588 IP Core

Features

  • Supports 10/100 Mbit/s half & full duplex modes
  • Delivered with PTP Version 1.0 and version 2.0 stack (Linux or Windows®)
  • Supports SPI cascade and independent slave mode
  • SPI data rates up to 20 Mbit/sec
  • 16-bit SPI data transfers, 32 bit interface to the internal SPI controller
  • 1 pps output
  • 1 period timer output with a period ranging from 14,000 sec down to 200 nsec.
  • 1 event input which draws a time stamp and stores it in the time stamp FIFO.
  • Events may be processed at a burst rate of 1 MHz
  • 1 trigger output signal which may be used to generate a signal transition at a given point in time
  • All event, period, and trigger signals are strictly synchronous to the internal high accuracy clock
  • Delivered with test bench, 100% code coverage guaranteed
  • Optional support of GPS timing receivers
  • RMII Interface option available upon request

For a complete list of features, download the datasheet.

Applications

  • Test and Measurement
  • Industrial Automation and Control
  • Telecom
  • Military
  • Power Industry

Implementation Results

The following are typical performance and utilization results.

Device Speed grade  Slices   LUTs    REGs   EBRs fMAX (MHz)

XP

-7

1668

1954

1726

4

75

XP2

-7

1552

1968

1591

4

125

Evaluation and licensing terms

Please contact Oregano directly at: http://www.oregano.at/en/index2.htm