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SGMII and Gb Ethernet PCS

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Overview

IPexpress User Configurable Logo The Lattice SGMII and Gb Ethernet PCS IP core implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX) specifications. The PCS mode is pin selectable. This IP core may be used in bridging applications and/or PHY implementations.

The Serial Gigabit Media Independent Interface (SGMII) is a connection bus for Ethernet Media Access Controllers (MACs) and Physical Layer Devices (PHYs) defined by Cisco Systems. It replaces the classic 22-wire GMII connection with a low pin count, 4-pair, differential SGMII connection. The classic GMII interface defined in the IEEE802.3 specification is strictly for Gigabit rate operation. However, the Cisco SGMII specification defines a method for operating 10 Mbps and 100 Mbps MACs over the interface. Moreover, the Cisco SGMII specification is
comprised of more than just a bus interface definition; it defines a bridging function between SGMII and GMII buses.

These applications can be completely implemented in LatticeECP3™, LatticeECP2M™ and LatticeSC™ Field Programmable Gate Array (FPGA) devices. As an example, Lattice has developed a reference design for a complete SGMII-to-(G)MII bridge. This reference design is included with the SGMII and Gb Ethernet PCS IP Core package and is described in detail in Appendix C.

The core can be instantiated, synthesized and simulated through ispLEVER® IPexpress™.

Application

 SGMII and Gb Ethernet PCS IP Reference Design

Key Features

  • Implements PCS functions of the Cisco SGMII Specification, Revision 1.7
  • Implements PCS functions for IEEE 802.3z (1000BaseX)
  • Dynamically selects SGMII/1000BaseX PCS operation
  • Supports MAC or PHY mode for SGMII auto-negotiation
  • Supports (G)MII data rates of 1Gbps, 100Mbps, 10Mbps
  • Provides Management Interface Port for control and maintenance
  • Includes Easy Connect option for seamless integration with Lattice's Tri-Speed MAC (TSMAC) IP core

Resource Utilization

 
LatticeECP31
Configuration SLICEs  LUTs   REGs  EBRs fMAX2
(MHz)
GMII Style RX CTC
Mode
FIFO Low
Threshold
FIFO High
Threshold

Classic

None

-

-

728

823 876 0 125

Classic

Static

16

32

809

935 977 1 125

Easy Connect

Static

240

260

681

787 821 1 125

Easy Connect

 Dynamic

-

-

697

797 852 1 125
1. Performance and utilization characteristics are using Lattice’s ispLEVER 7.2 SP1 software and Synplify 9.6L2 synthesis with an LFE3-70E-6FN484CES FPGA. When using this IP core in a different density, speed, or grade or in a different software version, performance may vary.
2. The SGMII requires operation at 125 MHz, therefore a higher frequency is not stated. However this core can easily attain frequencies above 140 MHz in a LatticeECP3 speed grade 6 device.
 
LatticeECP2M1
Configuration SLICEs  LUTs   REGs  EBRs fMAX2
(MHz)
GMII Style RX CTC
Mode
FIFO Low
Threshold
FIFO High
Threshold

Classic

None

-

-

726 823 876 0 125

Classic

Static

16

32

807 934 977 1 125

Easy Connect

Static

240

260

679 785 821 1 125

Easy Connect

 Dynamic

-

-

701 802 830 1 125
1. Performance and utilization characteristics are using Lattice’s ispLEVER 7.2 SP1 software and Synplify 9.6L2 synthesis with an ECP2M35E-5F672C FPGA. When using this IP core in a different density, speed, or grade or in a different software version, performance may vary.
2. The SGMII requires operation at 125 MHz, therefore a higher frequency is not stated. However this core can easily attain frequencies above 140 MHz in a LatticeECP2M speed grade 5 device.
 
LatticeSC1
Configuration SLICEs  LUTs   REGs  EBRs fMAX2
(MHz)
GMII Style RX CTC
Mode
FIFO Low
Threshold
FIFO High
Threshold

Classic

None

-

-

744 920 891 0 125

Classic

Static

16

32

702 865 856 1 125

Easy Connect

Static

240

260

583 727 700 1 125

Easy Connect

 Dynamic

-

-

714 903 845 1 125
1. Performance and utilization characteristics are using Lattice’s ispLEVER 7.2 SP1 software and Synplify 9.6L2 synthesis with an LFSC3GA25E-5FF1020C FPGA. When using this IP core in a different density, speed, or grade or in a different software version, performance may vary.
2. The SGMII requires operation at 125 MHz, therefore a higher frequency is not stated. However this core can easily attain frequencies above 200 MHz in a LatticeSC speed grade 5 device.

Ordering Information

LatticeECP3 GBE-SGMII-E3-U1
LatticeECP2M GBE-SGMII-PM-U1
LatticeSC GBE-SGMII-SC-U1

Evaluate: To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.
Purchase: To find out how to purchase the SGMII and Gb Ethernet PCS IP Core, please contact your local Lattice Sales Office.