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Direct Memory Access (DMA) is a technique for transferrring blocks of data between system memory and peripherals without the intervention of a microprocessor (e.g. system CPU). Using this technique reduces load on the system processing elements, while enabling much higher data throughput versus using standard processor reand and write transactions. Scatter-Gather DMA augments this technique by providing data transfers from on non-contiguous block of memory to another by means of a series of small contiguous block transfers. Lattice's Scatter-Gather DMA Controller IP core provides a master/slave interface, buffer descriptors, and DMA channels. The core is optimized to work with the Lattice PCI Express soft IP and MACO cores to achieve high-bandwidth PCI Express-based systems with DMA, but can also be used in any system application requiring high data throughput from a host system to a device, or a device to a host system.
Features
Top Level IP Support
- Supports up to 16 Physical Channels
- Up to 8 Sub-Channels per Physical Channel
- Supports simple DMA, Split Transfers, and Scatter-Gather DMA
- Four Priority Levels using Weighted Round-Robin Arbitration
- Supports Centralized and Distributed DMA Control Architectures
- Direct Interface to External RAM for Packet Buffering
- Autonomous and Hardware-Directed Retry
- WISHBONE Bus Widths from 8 to 128 Bits
- Supports WISHBONE Burst and Classic-Cycle Transfers
Performance and Resource Utilization
Results for LatticeSCM1
IPexpress User-Configurable Mode |
SLICEs |
LUTs |
Registers |
fMAX (MHz) |
16 channels, 8 sub-channels, 32-bit address width, 4K packet buffer size, 256 buffer descriptors |
2733 |
4234 |
1984 |
240 |
4 channels, 4 sub-channels, 32-bit address width, 4K packet buffer size, 16 buffer descriptors |
2061 |
3317 |
1308 |
246 |
8 channels, 4 sub-channels, 32-bit address width, 4K packet buffer size, 64 buffer descriptors |
2909 |
4774 |
1712 |
234 |
4 channels, 2 sub-channels, 32-bit address width, 4K packet buffer size, 16 buffer descriptors |
2052 |
3368 |
1239 |
250 |
1 Performance and utilization characteristics are generated using an LFSCM3GA-25E-6FF1020C with Lattice's ispLEVER 7.0 software. When using this IP core in a different density, package, speed, or grade within the LatticeSCM family, performance and utilization may vary.
Results for LatticeECPM/S1
IPexpress User-Configurable Mode |
SLICEs |
LUTs |
Registers |
fMAX (MHz) |
4 channels, 4 sub-channels, 32-bit address width, 4K packet buffer size, 16 buffer descriptors |
1959 |
3050 |
1307 |
158 |
1 Performance and utilization characteristics are generated using an LFE2M-35E-6F672C with Lattice's ispLEVER 7.0 software. When using this IP core in a different density, package, speed, or grade within the LatticeECP2M/S family, performance and utilization may vary.
Results for LatticeECP21
IPexpress User-Configurable Mode |
SLICEs |
LUTs |
Registers |
fMAX (MHz) |
8 channels, 4 sub-channels, 32-bit address width, 4K packet buffer size, 64 buffer descriptors |
2662 |
4205 |
1728 |
159 |
1 Performance and utilization characteristics are generated using an LFE2-35E-6F672C with Lattice's ispLEVER 7.0 software. When using this IP core in a different density, package, speed, or grade within the LatticeECP2 family, performance and utilization may vary.
Results for LatticeXP21
IPexpress User-Configurable Mode |
SLICEs |
LUTs |
Registers |
fMAX (MHz) |
4 channels, 2 sub-channels, 32-bit address width, 4K packet buffer size, 16 buffer descriptors |
1900 |
3063 |
1251 |
127 |
1 Performance and utilization characteristics are generated using an LFXP2-40E-6F6720C with Lattice's ispLEVER 7.0 software. When using this IP core in a different density, package, speed, or grade within the LatticeXP2 family, performance and utilization may vary.
Ordering Information
Part Numbers: For LatticeSC: DMA-SG-SC-U1 For LatticeECP2: DMA-SG-P2-U1 For LatticeECP2M: DMA-SG-PM-U1 For LatticeXP2: DMA-SG-X2-U1
To find out how to evaluate or purchase the Scatter-Gather DMA IP core, please contact your local Lattice Sales Office. |
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