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LatticeSCM PCI Express x1/x4 MACO

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 IPexpress User Configurable Logo PCI and its derivatives (PCI-X, PCI Express) are some of the most ubiquitous bus interfaces used in the technology industry (PCs, telecommunications, data communications, military, auto/ industrial and consumer). There are millions of existing PCI slots to be found everywhere in the home and industry. All these slots are slowly being upgraded to handle higher bandwidth data transfer using PCI Express.

PCI Express Logo Resized A PCI Express fabric is composed of point-to-point links that interconnect a set of components – composed of a Root Complex (RC), multiple Endpoints (I/O devices), Switches, and Bridges, all interconnected via PCI Express Links.  Each of the components of the topology is mapped in a single flat address space and can be accessed using PCI-like load/store accesses transaction semantics.

The LatticeSCM PCI Express x1/x4 MACO solution implements and endpoint device and is the industry’s first embedded ASIC-based programmable PCI Express solution.  It delivers the smallest and lowest power FPGA-based implementation for a complete x4 PCI Express endpoint, and is designed to be compliant to the PCI-SIG PCI Express Base Specification Revision 1.1. 


LatticeSCM PCI Express x1/x4 MACO Solution Highlights

  • Supported in LatticeSCM devices
  • Support for x1 and x4 PCI Express Endpoint
  • Majority of the PCI Express PHY Layer embedded in PCS block (Scrambler/Descrambler, Multi-Channel Alignment, Clock Tolerance Compensation)
  • Link Training and Status State Machine (LTSSM) and Link Width and Lane Negotiation State Machine
    • Included as Soft IP for the LatticeSCM25
    • Embedded as a MACO™ block in the SCM15, SCM40, SCM80, and SCM115 devices
  • Data Link Layer and PCI Express Framing implemented in flexiMAC™ MACO
  • Transaction Layer implemented as soft IP
  • Industry’s smallest sized (FPGA resource utilization) PCI Express solution
  • Smallest footprint (17x17 mm) FPGA-based PCIe solution based on LatticeSCM15-256-pin fpBGA (40% smaller than competition)
  • Lowest power PCI Express solution
  • IPexpress™ User-Configurable - configure the PCIe IP core, generate net lists and simulation files, and evaluate the core in hardware before license purchase
  • Compliant with PCI Express v1.1 Base Specifications
LatticeSCM PCI Express Stack Diagram

LatticeSCM PCI Express Stack Diagram

Physical Layer

  • 2.5Gbps CML Electrical Interface
  • PCI Express 1.1 Electrical Compliant
  • LatticeSCM Industry-leading Serialization and De-serialization (SERDES) block
  • 8b/10b Symbol Encoding/Decoding
  • Link State Machine for Symbol Alignment
  • Clock Tolerance Compensation Supports +/- 300ppm
  • Framing and Application of Symbols to Lanes
  • Data Scrambling/Descrambling
  • Lane-to-Lane De-skew
  • Signal Integrity options including Differential Output Voltage, Transmit Pre-Emphasis and Receiver Equalization
  • Link Training and Status State Machine (LTSSM) implemented as a MACO block (soft IP for LatticeSCM25 device)
    • Electrical Idle Generation
    • Receiver Detection
    • TS1/TS2 Generation/Detection
    • Lane Polarity Inversion
    • Link Width Negotiation
    • Higher Layer control to jump to defined states

Data Link Layer

  • Data Link Control and Management State Machine
  • Flow Control Initialization
  • Ack/Nak DLLP Generation/Termination
  • Power Management DLLP Generation/Termination through simple user interface
  • LCRC Generation/Checking
  • Sequence Number Appending/Checking/Removing
  • Retry Buffer and Retry Management

Transaction Layer

  • Supports all types of TLPs (Memory, I/O, Configuration, and Message)
  • Power Management User Interface to Easily Send Power Messages
  • Optional ECRC Generation/Checking
  • 512, 1k, 2k, or 4k Maximum Payload Size

Configuration Space Support

  • Implements the following:
    • PCI-Compatible Type 0 Configuration Space Registers (0x0-0x3C)
    • PCI Express Capability Structure Registers
    • Power Management Capability Structure Registers
    • MSI Capability Structure Registers
    • Device Serial Number Capability Structure
    • Advanced Error Reporting Capability Structure
  • Remaining Configuration Requests can be handled by the user or terminated by the core

Top Level IP Support

  • 250 MHz Reference Clock Input (FPGA PLL converts 100 MHz Reference Clock to 250 MHz if required)
  • 125 MHz 64-Bit Data Path User Interface for both x1 and x4
  • In Transmit, User Creates TLPs Without ECRC, LRCR or Sequence Number
  • In Receive, User Receives Valid TLPs Without ECRC, LCRC, or Sequence Number
  • Credit Interface for Transmit and Receive for PH, PD, NPH, NPD, CPLH, CPLD Credit Types
  • Upstream/Downstream, Single Function Endpoint Topology
  • Higher Layer Control of LTSSM via Ports
  • Access to Select Configuration Space Information via Ports
  • Supported in LatticeSCM -5, -6, and -7 Speed Grades in both 1.2 V and 1.0 V (up to 50% power reduction)

 

PCI Express IP Users Manual

The LatticeSCM MACO PCI Express IP Core User Manual is available here.

PCI Express Evaluation Boards

Three LatticeSCM evaluation boards are available for PCI Express evaluations, one with a x1 PCI Express connector (for x1 PCI Express evaluations), one with a x4 PCI Express connector (for x1 and x4 PCI Express evaluations) and one with a x8 PCI Express connector (for x1, x4, and x8 PCI Express evaluations). More details of these boards are available here:

PCI Express Demo Package

PCI Express Demo Setup (thumbnail)

PCI Express Demo Setup [Click to enlarge]

Lattice’s PCI Express solutions for LatticeSCM come with a complete demo package. The demo package for the LatticeSCM PCI Express solution includes the following:

WINDOWS

LINUX

ispLever Demo Project Directories

 

PCI Express Throughput Demo Package

Lattice’s PCI Express solutions for LatticeSCM also include a PCI Express Throughput demo package.  This demo uses the Lattice PCI Express IP Core to show the performance of the PCI Express system from the endpoint to the system memory. The LatticeSCM PCI Express throughput demo package includes the following:

 

PCI Express and Scatter Gather DMA (SG-DMA) Demo Package

Lattice’s PCI Express solutions for LatticeSCM also include a full-featured demo including the LatticeSCM PCI Express Core and the LatticeSCM SG-DMA IP. This demo uses the LatticeSCM PCI Express IP Core and the LatticeSCM SG-DMA IP Core to move data (DMA) from the PCI Express card to the system memory. The LatticeSCM PCI Express and Scatter Gather DMA demo package includes the following:

Performance and Resource Utilization

Results for LatticeSCM-15/40/80/1151
IPexpress User-Configurable Mode Slices LUTs Registers sysMEM EBRs MACO Blocks
Config 1 - Soft LTSSM 5678 8122 6064 11 1
Config 2 - Hard LTSSM 3811 4701 4696 11 2

  1 Performance and utilization characteristics are generated using LFSC3GA80E-6FC1704C with Lattice's ispLEVER® v7.0 software.  When using this IP core in a different density, speed, or grade within the LatticeSCM family, performance and utilization may vary.  Soft LTSSM is not required for LFSC3GA15/40/80/115 devices as hard LTSSM MACO is available in these devices.  Utilization and performance results for PCI Express x1 and x4 mode are identical in LatticeSCM devices.

Results for LatticeSCM-251
IPexpress User-Configurable Mode Slices LUTs Registers sysMEM EBRs MACO Blocks
Config 1 - Soft LTSSM 5678 8122 6064 11 1

  1 Performance and utilization characteristics are generated using LFSC3GA25E-6FF1020C with Lattice's ispLEVER 7.0 software.  When using this IP core in a different density, speed, or grade within the LatticeSCM family, performance and utilization may vary.  Soft LTSSM is required for LFSC3GA25 devices as hard LTSSM MACO is not available for these devices.   Utilization and performance results for PCI Express x1 and x4 mode are identical in LatticeSCM devices.

Licensing

All LatticeSCM MACO IP is free of charge through ispLEVER.  However a license key is required to enable simulation and bitstream generation. Please contact your local Lattice Sales Office to obtain your MACO IP license key.