LatticeMico32 DDR SDRAM and VGA Monitor Demo

Overview

The demonstration focuses on the LatticeMico32 Development Board’s VGA interface, with a DDR SDRAM module used for executing code and serving as video memory. The LatticeMico32 processor, a WISHBONE master, writes to this video memory, and an incorporated VGA controller, also a WISHBONE master, reads from this video memory. The VGA controller is implemented in VHDL language, and this demonstration shows how to incorporate VHDL custom components into the Verilog-language LatticeMico32 platform framework.

The demonstration runs on a LatticeMico32 Development Board for LatticeECP connected to a VGA monitor.

Features

• Colocation of the FPGA bitstream and the software application in the SPI configuration flash.
• Processor wake-up and execution of boot code from the SPI flash.
• Processor executes code from a copy stored to the external DDR SDRAM.
• The DDR SDRAM is partitioned into video and software code sections.
• Processor updates the contents of the video memory while the VGA master interface reads the video memory contents.

Documentation

LatticeMico32 DDR SDRAM Demo User's Guide

Demo Package

The demo package is released as a zipped file. Simply download the file and unzip it. Other Lattice tools that may be needed are ispVM^® System software to download the bitstream, and ispLEVER^® design tools if any changes to the design are to be made

LatticeMico32 DDR SDRAM Demo

To find out more about this demo or about the DDR SDRAM Controller IP Core, please contact your local Lattice Sales Office