DDR SDRAM Controller - Non-Pipelined

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Overview

This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined version. DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.

The DDR SDRAM Controller is a parameterized core giving users the flexibility for modifying data widths, burst transfer rates and CAS latency settings in a design. In addition, the DDR core supports intelligent bank management, which is done by maintaining a database of "all banks activated" and the "rows activated" in each bank. With this information, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write commands issued to the DDR SDRAM.

Features

Performance of Greater than 133MHz (266 DDR)
Interfaces to JEDEC Standard DDR SDRAMs
Supports DDR SDRAM Data Widths of 16, 32 and 64 bits
Supports up to 8 External Memory Banks
Programmable Burst Lengths of 2, 4, or 8
Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0
Byte-level Writing Supported
Supports Power-down and Self Refresh Modes
Automatic Initialization
Automatic Refresh During Normal and Power-down Modes
Timing and Settings Parameters Implemented as Programmable Registers
Complete Synchronous Implementation

Evaluation Configurations

Performance and Utilization for ORCA 4¹
Parameter File	ddrct_np_o4_1_008.lpc
Core Configuration	Generic User I/F (non-pipelined version)
ORCA 4 PFUs²	283
LUTs	703
Registers	1044
Dist. RAM³	3
f_MAX (MHz)	133
External Pins	239
sysMEM^TM EBRs	N/A

¹ Performance and utilization characteristics are generated using an OR4E023BM416-DB in Lattice’s ispLEVER v.3.1 software. When using this IP core in a different density, package, speed, or grade within in the ORCA 4 family, performance may vary.
² PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.³ Dist. RAM = distributed memory.

Performance and Utilization for LatticeECP and LatticeEC FPGAs¹
Parameter File	ddrct_np_e2_3_005.lpc
SLICEs	918
LUTs	805
Registers	1369
I/Os	229
sysMEM^TM EBRs	0
f_MAX (MHz)	200 MHz (400 DDR)

¹ Performance and utilization characteristics are generated using LFEC20E-5F672C in Lattice's ispLEVER v.5.0 software. When using this IP core in a different density, speed, or grade within the LatticeECP/EC family, performance may vary.

Performance and Utilization for LatticeXP¹
Parameter File	ddrct_np_xm_3_005.lpc
SLICEs	857
LUTs	807
Registers	1237
I/Os	229
sysMEM^TM EBRs	0
f_MAX (MHz)	166 MHz (333 DDR)

¹ Performance and utilization characteristics are generated using LFXP10E-5F388C in Lattice's ispLEVER v5.0 software. When using this IP core in a different density, speed, or grade within the LatticeXP family, performance may vary.

Ordering Information

Part Numbers:
For ORCA 4: DDRCT-NP-O4-N1
For LatticeECP/EC: DDRCT-NP-E2-N3
For LatticeXP: DDRCT-NP-XM-N3

To find out how to purchase the 32 Bit PCI Target IP Core, please contact your local Lattice Sales Office.