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32 Bit PCI Target

In Detail

Overview

IPexpress User Configurable LogoPeripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommunications, embedded systems, high performance peripheral cards, and networking.

Lattice's PCI IP core provides an ideal solution that meets the needs of today's high performance PCI applications. It is fully compliant with the PCI Local Bus Specification, revision 2.2 for speeds up to 66MHz. The PCI core provides a customizable 32/64-bit master/target or target solution. The core bridges the gap between the PCI interface and a specific design application, providing an integrated PCI solution. The PCI solution allows designers to focus on the application rather than on the PCI specification, resulting in a faster time-to-market.

PCI-SIG LogoThe Lattice PCI offering is available in a number of configurations covering 32-bit PCI, 64-bit PCI, 32-bit local bus, 64-bit local bus, master/target and target applications. In this document, details of 64-bit operation and master operation only apply when relevant. The appendix to the user's guide shows what cores are available on which devices.

PCI Block Diagram 32-bit, 64-bit

Features

  • Available as 32/64-Bit PCI Bus and 32/64-Bit Local Bus
  • PCI SIG Local Bus Specification, Revision 3.0 Compliant
  • 64-Bit Addressing Support (Dual Address Cycle)
  • Capabilities List Pointer Support
  • Parity Error Detection
  • Up to Six Base Address Registers (BARs)
  • Fast Back-to-Back Transaction Support
  • Supports Zero Wait State Transactions
  • Special Cycle Transaction Support
  • Customizable Configuration Space
  • Up to 66MHz PCI
  • Fully Synchronous Design

Performance and Resource Utilization

LatticeECP31
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 425 623 422
- 48
33
32-bit Target 66 MHz 527
845
443 -
48
66

1. Performance and utilization characteristics are generated using LFE3-95E-7F1156CE, with Lattice ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeECP3 family, performance and utilization may vary.

LatticeECP2M1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 534 626 422 - 48
33
32-bit Target 66 MHz 552 847 443 -
48
66

1. Performance and utilization characteristics are generated using LFE2M-35E-6F672C, with Lattice's ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeECP2M family, performance and utilization may vary.

LatticeECP21
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 534 626 422 - 48
33
32-bit Target 66 MHz 552 847 443 -
48
66

1. Performance and utilization characteristics are generated using LFE2-20E-6F672C, with Lattice's ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeECP2 family, performance and utilization may vary.


LatticeEC/P1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 528 617 422 -
48 33
32-bit Target 66 MHz 551 846 443 -
48 66

1. Performance and utilization characteristics are generated using LFEC33E-5F672C, with Lattice's ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeECP/EC family, performance and utilization may vary.


LatticeSC1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 373 531 421 - 48
33
32-bit Target 66 MHz 525 825 443 -
48
66

1. Performance and utilization characteristics are generated using LFSC3GA25E-6F900C, with Lattice's ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeSC family, performance and utilization may vary.


LatticeXP21
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 534 626 422 - 48
33
32-bit Target 66 MHz 552 847 443 -
48
66

1. Performance and utilization characteristics are generated using LFXP2-17E-6F484C, with Lattice's ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeXP2 family, performance and utilization may vary.

LatticeXP1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 528 617 422 - 48
33
32-bit Target 66 MHz 551 846 443 -
48
66

1. Performance and utilization characteristics are generated using LFXP20C-5F484C, with Lattice's ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeXP family, performance and utilization may vary.

LatticeMachXO1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs
External
Pins
fMAX (MHz)
32-bit Target 33 MHz 315 617 422 - 48
33
32-bit Target 66 MHz 454 846 443 -
48
66

1. Performance and utilization characteristics are generated using LCMXO2280C-5FT324C, with Lattice's ispLEVER 7.2 SP2 software. When using this IP core in a different density, speed, or grade within the MachXO family, performance and utilization may vary.


Ordering Information

Family Bus Width Bus Speed Target
Part Number
LatticeECP3 32-bit 33MHz, 66MHz PCI-T32-E3-U6
LatticeECP2M 32-bit 33MHz, 66MHz PCI-T32-PM-U6
LatticeECP2 32-bit 33MHz, 66MHz PCI-T32-P2-U6
LatticeECP/EC 32-bit 33MHz, 66MHz PCI-T32-E2-U6
LatticeSC 32-bit 33MHz, 66MHz PCI-T32-SC-U6
LatticeXP2 32-bit 33MHz, 66MHz PCI-T32-X2-U6
LatticeXP 32-bit 33MHz, 66MHz PCI-T32-XM-U6
MachXO 32-bit 33MHz PCI-T32-XO-U6

IP Version: 6.2
Evaluate: To download a full evaluation version of this IP, go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP cores and modules available for download are visible on this tab.
*PCI cores for ORCA and ispXPGA,devices are supported by the Lattice factory-configurable design flow.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.