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Overview
 The 10Gb Ethernet Media Access Ccontroller (MAC) transmits and receives data between a host processor and an Ethernet network. The main function of the 10Gb MAC is to ensure that the Media Access rules specified in the IEEE802.3ae standard are met while transmitting a frame of data over Ethernet. On the receive side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through a FIFO interface.
Features
- Compliant to IEEE802.3ae-2002 standard
- 64-bit wide internal data path operating at 156.25 MHz
- XGMII interface to the PHY layer
- XAUI interface to the PHY layer (using PCS/SERDES external to the core)
- Simple FIFO interface with user’s application
- Multicast address filtering
- Transmit and receive statistics vector
- Optional MDIO Controller
- Programmable Inter Frame Gap
- Supports:
- Full duplex operation
- Flow control using PAUSE frames
- VLAN tagged frames
- Automatic padding of short frames
- Optional FCS generation during transmission
- Optional FCS stripping during reception
- Jumbo frames of any length
- Inter frame Stretch Mode during transmission
The 10GMAC is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
Performance and Resource Utilization
Results for LatticeSC/M1
|
MDIO
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Multicast Address Filtering |
SLICEs |
LUTs |
Registers |
External Pins2 |
sysMEM EBRs |
fMAX (MHz) |
|
No
|
No
|
2541
|
3103
|
3011
|
74
|
6
|
170
|
|
Yes
|
Yes
|
3852
|
4950
|
4925
|
76
|
6
|
170
|
1 Performance and utilization characteristics are in Lattice's ispLEVER® v6.0 SP1 software. When using this IP core in a different density, speed, or grade within the LatticeSC family or in a different software version, performance may vary.
2 The 10GMAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O buffers integrated in the LatticeSC series FPGA. Thus, the application implementing the 10GMAC specification will utilize I/O pins.
Results for LatticeECP2/S1
|
MDIO
|
Multicast Address Filtering
|
SLICEs |
LUTs |
Registers |
External Pins2 |
sysMEM EBRs |
fMAX (MHz) |
|
No
|
No
|
2639
|
3319
|
2993
|
74
|
6
|
170
|
|
Yes
|
Yes
|
2845
|
3454
|
3171
|
76
|
6
|
170
|
1 Performance and utilization characteristics are in Lattice's ispLEVER® v6.0 SP1 software. When using this IP core in a different density, speed, or grade within the LatticeECP2 family or in a different software version, performance may vary.
2 The 10GMAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O buffers integrated in the LatticeECP2 series FPGA. Thus, the application implementing the 10GMAC specification will utilize I/O pins.
Results for LatticeECP2M/S1
|
MDIO
|
Multicast Address Filtering
|
SLICEs
|
LUTs
|
Registers
|
External Pins2
|
sysMEM EBRs
|
fMAX (MHz) |
|
No
|
No
|
2625
|
3118
|
2989
|
74
|
6
|
170
|
|
Yes
|
Yes
|
2845
|
3430
|
3169
|
76
|
6
|
170
|
1 Performance and utilization characteristics are in Lattice's ispLEVER® v6.1 software. When using this IP core in a different density, speed, or grade within the LatticeECP2M family or in a different software version, performance may vary.
2 The 10GMAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O buffers integrated in the LatticeECP2M series FPGA. Thus, the application implementing the 10GMAC specification will utilize I/O pins.
Ordering Information
Part Numbers:
For LatticeSC: ETHER-10G-SC-U3
For LatticeECP2: ETHER-10G-P2-U3
For LatticeECP2M: ETHER-10G-PM-U3
To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.
To find out how to purchase the 10GMAC IP Core, please contact your local Lattice Sales Office. |
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