High Performance DES and Triple-DES Cores

These high performance cores from Helion have been highly optimised for use in FPGA, and implement the DES and triple-DES encryption standards, as described in NIST Federal Information Processing Standard (FIPS) publication 46-3.

Two versions are available, each offering different trade-offs between area and speed. The smallest solution is a one-round-per-clock solution, which has been very carefully designed for minimum area in FPGA. The faster variant is somewhat different to most others commercially available in that it operates at a rate of two-rounds-per-clock. This results in a core which will run significantly faster for a given gate-count, so for high performance designs, where either speed is essential or space is limited, these cores may be the perfect solution.

Features

• Implements DES and Triple-DES to NIST FIPS publication 46-3
• Two versions available; user can choose best balance of speed and size for application
• Very fast operation – Single DES Encryption/Decryption takes only 9-clock cycles in fastest version
• Same core offers dynamically selectable single DES/triple DES and encrypt/decrypt modes
• All DES operating modes easily implemented (eg. ECB, CBC, OFB, CFB, CTR, CBC-MAC)
• Simple external interface
• Highly optimised for use in each individual FPGA technology

Ordering Information

For more information on this IP core or for pricing and availability please contact Helion Technology.