iCEblink40LP1K Evaluation Kit

A low-cost platform for evaluating and developing with the low-power iCE40LP1K FPGA. The board provides access to general-purpose I/O and includes capacitive-touch buttons and LEDs. The board is powered and programmed via USB. An on-board microcontroller enables two-way communication with the iCE40LP1K FPGA.

The free iCEcube2 development tool controls programming, accesses virtual I/O functions, and runs the included demos. The tools can be downloaded from the Lattice website.

Features

  • Low power, small footprint iCE40LP1K FPGA in an 84-pin QFNS package
  • USB programming, debugging, virtual I/O functions and power supply
  • Four user LEDs
  • Four capacitive-touch buttons
  • 3.3 MHz clock source
  • 1 Mbit SPI serial configuration PROM
  • Supported by iCEcube2 design software
  • 63 LVCMOS/LVTTL (3.3V) digital I/O connections on 0.1” through-hole connections
  • Supports third-party I/O expansion boards and modules, including 3.3V Arduino Shield boards (requires additional sockets, not supplied)

Jump to

Kit Contents

  • iCEblink40 LP1K Board
  • USB Mini Cable for power & programming
  • QuickStart Guide

Board Photos

Side View

Click image to enlarge

Top View

Click image to enlarge

Bottom View

Click image to enlarge

Ordering Information

  • This product is no longer available for purchase
  • The information provided here is for reference purposes only
  • Reference number: ICE40LP1K-BLINK-EVN

Documentation

Quick Reference
Technical Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
CapSense Demo for iCEblink40 Evaluation Kits - User's Guide
UG64 1.0 10/17/2012 PDF 2.1 MB
iCEblink40-LP1K Evaluation Kit User's Guide
Includes schematics in .pdf format
EB75 01.1 9/18/2012 PDF 3.3 MB
Programming Cable User Guide
Describes the features and recommended usage guidelines of Lattice ispDOWNLOAD Cables.
FPGA-UG-02042 26.4 5/29/2020 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
CapSense Demo for iCEblink40 Evaluation Kits - User's Guide
UG64 1.0 10/17/2012 PDF 2.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCEblink-LP1K Default Design Files
This is a .zip of the default design that is programmed onto each new board. This include the programming file and the Verilog source.
7/18/2013 RAR 13.8 KB
iCEblink40-LP1K Layout and Schematic Source
This zip file contains the layout and schematic source files for the iCEblink40-LP1K board, in Altium source format.
9/12/2012 ZIP 238.4 KB
iCEblink40-LP1K Gerber Files
Gerber files of the iCEblink40-LP1K PCB.
9/12/2012 ZIP 112 KB
CapSense Demo for iCEblink40-LP1K Evaluation Kit
2.0 7/18/2013 RAR 1.5 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Support

Technical Support

Need Help? We're Here to Assist You

Quality & Reliability

Reference Material to Help Answer Your Questions

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.