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FAQ

Radiant: How do you hide warning messages?

Description:To hide all warnings, simply click the "WARNING: " button to hide all the warnings. This follows for hiding all errors, criticals, etc.For hiding specific types of warnings, you may filter them by right-clicking the warning and then Filter. You can…

FAQ

Diamond: WARNING - Unsupported property ASYNC_REG found

Description:The Async_Reg is an unsupported property in the software which is why this placing attribute is ignored.What we could suggest is that you can add an HGROUP attribute in the RTL code.For example, a design that contains double synchronizers for clock domain crossing.Solution:By adding the…

FAQ

Lattice Radiant: What does this warning mean "Generated_clock: not connect to any master clock pin."?

Description:The user encounters a WARNING message shown below whenever they utilize a PLL IP. "Generated_clock: not connect to any master clock pin."Solution:The warning implies that the timing engine is indicating that there is no clock at the source pin. The user needs to define a…

FAQ

Radiant: Is there any documentation that explains the error and warning messages produced in Radiant?

Description:We do not have documentation on the errors or warnings generated by Radiant.Usually, the errors and warnings are described in Radiant software itself.In some cases, warnings and errors are not too verbose for the user but we are continuously improving this feature.If…

FAQ

Lattice ispLEVER: ispLEVER issued warning for a design with EBR in ASYNC Reset mode

Lattice ispLEVER: This is due to a hardware restriction and there is a possibility that you may destroy the memory content if this operation isn't performed properly. This is documented in LatticeECP2/M Family Data Sheet (DS1006.pdf, Page 2-20) and LatticeSC/M Data Sheet (DS1004.pdf, Page 2-15). We…

FAQ

Diamond 3.13 and below: warning occurs when generating VHDL simulation file WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. An

Description:When generating a post-synthesis VHDL simulation file in Diamond, the warning below will occur:"WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. Any names following the first will be uniquified."Solution:This is a…

FAQ

ispLEVER Classic: What is the meaning of the ispLEVER Classic warning "P38088: Balanced partitioning turned off"?

This warning indicates that the balanced partitioning strategy of the fitter is turned off in order to find a successful fit for the design. Balanced partitioning is a method to keep the CPLD utilization uniform across the device. Therefore, if the fitter successfully fits the design, the…

FAQ

Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature? 

Description:When user design is compiled (Synthesis --> Bitstream) a Warning shown below is encountered WARNING -Security project file open Error! Security feature is turned OFF!Solution:The warning is valid and is just providing message that the design/project does not have any…

FAQ

Lattice IspLever: What does a warning about 'potential circuit loops' mean and how can I find them?

Description:When doing a 'map timing checkpoint' in ispLEVER, you might see the following message: "1 potential circuit loop found in timing analysis" Solution:This message is related to conditions being met to latch in data where "potential" indicates that there may or may not be asynchronous…

FAQ

PAC-Designer:  Why does user design fail to compile with a Warning 1211: Generate NAF file failed?

If the user Power Manager II design fails to compile and gives a Warning 1211 in the error message window it may be caused by using spaces or periods in the project file name or path name.AHDL2BLF; ABEL-HDL ProcessorPAC-Designer 6.30 Copyright(C), 1992-2005, Lattice Semiconductor Corporation.…

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Data Center Systems – Storage Systems

FAQ

All FPGA: What does the inferred clock warning "WARNING - MT420 |Found inferred clock...with period...Please declare a user-defined clock on..."?

Description:WARNING - MT420 |Found inferred clock cpu_pll_ipgen_lscc_pll_Z21_layer0|clkop_o_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net cpu_system_i.cpu_pll_i.lscc_pll_inst.clk_50M.  Solution:The warning means that the user has not defined the PLL…

FAQ

Diamond: Why does the design trigger warning messages stating Edge or Primary clock is un-routable, occupied and uses general routing, or are not placed on sweet site?

Occasionally in congested designs a conflict occurs resulting in an unroutable condition during the Place and Route (PAR) phase of a design. The conflict can be due to components that have been placed by user constraints, or by the decisions made by the placement tool.  It may become necessary for a…

FAQ

What is the meaning of this warning in Active-HDL:Warning: DAGGEN_0523: The source is compiled without the -dbg switch. Line breakpoints, code coverage, and assertion debug will not be a

This is a normal warning that is generated when you are not applying code coverage etc. while simulating the design in Aldec Active-HDL with minimum switches. In normal RTL simulations you don't need the debug switch and this warning will not effect your simulations.For more…

FAQ

Avant-X 25G Ethernet: Why does Lattice Radiant Software show a critical warning when designing the 25G Ethernet IP on Avant-X FPGA with -2 and -1 performance grades?

Description: The supported performance grade for Avant-X 25G Ethernet IP is -3 (fastest).Radiant's critical warning as below will appear when using -1 and -2 performance grade devices.This speed grade limitation applies only to Avant-X 25G Ethernet IP. There is no speed grade limitation to…

FAQ

Diamond / All FPGA: Why does the following warning message appear in Spreadsheet View of the software when a single-ended clock pin in the design is assigned to a Primary Clock port?

Description:WARNING - Warning -The clock port [RCLK] is assigned to a non clock dedicated pin [D14], which might affect the clock performance.Solution:In the Spreadsheet View of Lattice Diamond Software, if the clock pin is assigned to a complementary pin of a Primary clock, this…

FAQ

Lattice ispLEVER: Place and Route: Why do I get a warning message about an edge clock not on a sweet site during place and route when targeting an SC/M?

Lattice ispLEVER: Place and Route: In congested designs a conflict may occur resulting in an unroutable condition in PAR. This may be due to user constraints or unfavorable placement of logic by the software. Depending on the size and complexity of a design, it may become necessary to specify the…

FAQ

Diamond / Synplify Pro: Does the warning "@W:MT246 Blackbox EHXPLLJ is missing a user supplied timing model" have any negative effect on the timing analysis and optimization, or the Quality of

Description:In Diamond and when using Synplify Pro as the synthesis tool, this warning "@W:MT246 Blackbox EHXPLLJ is missing a user supplied timing model" can occur when performing synthesis with an instantiation of any IP core using IPexpress. Solution:The Synplify Pro synthesis tool does…

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Lattice Releases Next-Generation FPGA Software for Development of Broad Market Low Power Embedded Applications

Lattice today announced the release of its new FPGA software, Lattice Radiant™, targeted for the development of broad market low power embedded applications.

FAQ

[Lattice Diamond]: Why do I get the following warning in Lattice Diamond Tool when I try to use a primary clock site pin as a secondary clock input. ?Warning : "The driver of secondary c

The Warning is just to warn the user that the signal is using general routing instead of dedicated clock resource.For general routing, the tool usually takes much longer delay. And we don't recommend usage of general routing on clock signals. So it will be the best if user can move the pin…