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SERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board User's Guide

The SERDES Eye/Backplane Demo installs into the default location of C:\Lattice_DevKits\DK-ECP3-SERDES- 010\. However, you can install the demo files in a directory of your choice. The demo directory includes the follow- ing in Windows and root/DK-ECP3-SERDES-010 in Linux: �…

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What is SERDES and Why is it Used?

Understanding the basics of SERDES and its usage in FPGAs

Board

LatticeECP2M SERDES Evaluation Board

No longer available - for reference only. For development and evaluation of the SERDES performance of the LatticeECP2M FPGA (LFE2M50E-6F672C) + SMA for SERDES.

Board

High-Speed SERDES Briefcase Board

No longer available - for reference only. For evaluation of the high-speed SERDES capabilities of the ORT82G5 or ORSO82G5 devices + 8 x 3.7Gbits/sec accessible.

FAQ

[LatticeECP2/M] Can the SERDES input voltage threshold be modified to force the SERDES into a reset state?

The SERDES input voltage threshold cannot be modified.  But you can adjust the SERDES register RLOS_HSET(increase or reduce the threshold) which is described on page 72 of the LatticeECP2M SERDES/PCS Usage Guide, TN1124If the SERDES input voltage is out of the threshold…

FAQ

Is it possible to reverse SERDES XAUI lanes on a LatticeSC/M flexiPCS?

It is not possible to swap/reverse SERDES XAUI lanes on a LatticeSC/M flexiPCS for the following reasons: 1. The PCS won't be able to support some of the XAUI PCS special functions like section 48.2.4.5 (Link status ) , 48.2.6.4 (Link status reporting) and Sequence ordered_sets in the IEEE…

FAQ

LatticeECP3:  What is the depth of Serdes down/up-sampling FIFOs?

The depth of Serdes down/up-sampling FIFOs is four. It is very shallow. It requires that the read and write clock to them come from the same clock source. Only phase difference between read and write clocks is allowed in order to make these FIFOs function correctly. If there is any ppm…

FAQ

Simulation: Steps to compile/elaborate a SERDES based design in NC-Verilog?

Simulation: Compiling/elaborating a SERDES based design requires pre-compiling the SERDES model.  Follow the steps below to compile the Lattice SERDES model, revise your library definition file, and compile and elaborate your design.Unzip the provided SERDES model.  The…

FAQ

Are there any pins that can't be used when the SERDES is being used?

There are placement rules regarding keep-out areas near VCCRX and VCCTX, as well as pins adjacent to operational SERDES Quads. These are known as "aggressor I/O pins".If you are not using certain SERDES Quads, it is perfectly acceptable to use the pins in the keep out areas of the…

FAQ

What is the SERDES channel to channel transmit skew for the LatticeSC?

The LatticeSC SERDES has a channel to channel transmit skew of only 200ps across all channels in the device. This tight transmit skew allows the LatticeSC device to be used in a number of parallel SERDES based applications such as PCI Express and SFI-5. There are two important…

FAQ

LatticeECP3: In LatticeECP3, is it possible to change the Serdes mode from 8b/10b to 10b Serdes mode via the SCI on the fly when the data rates are same for both mode?

If all control registers bits setting are correct for both modes, it will work. To get the control registers bit setting information for each mode, you can use ORCAstra. You will have to apply reset after changing the mode.

FAQ

Will all speed grades of the LatticeECP2/M and LatticeECP3 support the SerDes at 3.125 Gbps?

Yes, the SerDes/PCS is an embedded block and the performance is independent of speed grade. Only the FPGA core logic is affected by speed grade.

FAQ

LatticeECP3: Does Lattice provide IBIS model for SERDES inputs and outputs of LatticeECP3?

Currently Lattice does not provide LatticeECP3 IBIS model for SERDES input and outputs such as HDINP/N and HDOUTP/N. Alternatively, we recommended you use the LatticeECP3 HSPICE IO Kit to reach their simulation goals. The Lattice HSPICE IO Kit is available under non-disclosure agreement…

FAQ

LatticeECP3: Are there any special considerations to interface the LatticeECP3 SERDES to standard SFP transceiver modules?

Referring to the Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA), the LatticeECP3 SERDES inputs and outputs are compatible with the specification. This allows for a very clean interface between the module and the fpga. The RD-/+ are the differential receiver outputs…

FAQ

LatticeECP3: What are minimum and maximum voltage levels of SERDES inputs?

You may refer to Table 3-9 (Serial Input Data Specifications) of LatticeECP3 Family data sheet. The minimum and maximum voltage levels of LatticeECP3 SERDES inputs are defined as input levels (VRX-IN) in LatticeECP3 data sheet. The minimum input voltage can be as low as 0V. The maximum…

FAQ

ECP3 : How long does it take for the SerDes TX PLL to lock?

For both LatticeECP2M and LatticeECP3, the SerDes TX PLL Lock time depends on the value of PLL_LOL_SET and the quality of the TX reference clock (REFCLK). The times given below are measured from release of Quad Reset assuming that REFCLK is stable.PLL_LOL_SET = "00" requires 1.4 million Unit…

FAQ

LatticeECP3: When is it appropriate to use dc-coupling with the LatticeECP3 SERDES reference clock?

The dedicated SERDES reference clock inputs for the LatticeECP3 include default ac-coupling capacitors and optional dc-coupled connections. This dc-coupled connection is available only in the case where an external ac-coupling capacitor is being placed on the board. It is not recommended to…

FAQ

Certus-NX: What to do with an unused SerDes power supply and other pins?

Description:When SerDes is not used, there are proper states for unused pin.Solution:Connect VSSSD, Rx Differential Inputs, SD_EXTx_RefCLKx, SDQx_RefCLKx, and RefRETx to board ground. Then, leave VCCSD0, VCCPLLSD0, VCCAUX, SDx_REXT and Tx Differential Pair outputs open or unconnected.

FAQ

CertusPro-NX SERDES: Should the unused channel/s on a SerDes Quad be powered?

Solution:The only requirement is to power-up the channel 1 of the used quad even if this channel is unused.The rest of the unused channel/s can be left floating or not connected. Refer to Section 13.5 of the CertusPro-NX SerDes/PCS User Guide (FPGA-TN-02245)Note section: Channel 1 of the used…

FAQ

LatticeECP2/M: Where can I find the Serdes Reset RTL code ?

The Reset Sequence code for ECP2/M is included in Serdes demo package.http://www.latticesemi.com/dynamic/view_document.cfm?document_id=24513