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IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.

FAQ

RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU

RISC-V cacheable address is configurable in MC, and fixed in RX.The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen.This imply that CPU store operation will write to destination, while load operation…

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

IP Core

RISC-V Nano CPU IP Core

The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.

Reference Design

RISC-V RX and LPDDR4 Memory Controller Reference Design

RISC-V RX & LPDDR4 Memory Controller Reference Design shows usage of the RISC-V RX soft IP & LPDDR4 memory controller in Lattice Avant™ & CertusPro™ NX.

Webpage

See Lattice at RISC-V Summit 2018

Visit Lattice to learn about ultra-low power implementations of RISC-V processor based on the Lattice iCE40 UltraPlus FPGA.

IP Core

NOEL-V RISC-V Processor IP Core

The NOEL-V is a VHDL model of a processor that implements the RISC-V architecture, which can be configured to conform to the RV32 or RV64 architectures.

IP Core

RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.

Document

XPIO 110GXS Data Sheet

Data Sheet PDF 350.5KB

Document

Adding Scalable Power and Thermal Management to Nexus FPGAs

Application Note FPGA-AN-02079 1.0 PDF 1.3MB

Document

ispClock5400D Evaluation Board, User Guide

Figure 1. ispClock5400D Evaluation Board Software Requirements Install the following software before you begin developing designs for the ispClock5400D Evaluation Board: �PAC-Designer ® 5.2 (ispClock5406D support) � Optional: ispLEVER ® /Pro (LatticeECP3 support) � Optional: ispVM™ System 17.5 4…

IP Core

RISC-V Single Core Linux (SCL) Processor

RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.

FAQ

RISC-V CPU IP Core: Do Lattice RISC-V supports exception trap handler when writing data to an invalid address?

Description: RISC-V SM(v1.5)/MC(v2.5) CPUs currently only support trap handler for read access error.When CPU read from an invalid instruction/data address range, it will cause an exception which trigger the trap handler.However, if CPU write to an invalid data address range which trigger a…

FAQ

RISC-V MC/RX/SM IPs: Does the RISC-V CPU reset (i.e. system_resetn_o) signal asynchronous or synchronous?

Solution:If the debug is enabled, it is synchronous. If not, then it is controlled by an input reset (either synchronous or asynchronous) and by watchdog timer (synchronous). This is valid for the RISC-V RX.Unfortunately RISC-V MC and SM does not have an integrated watchdog timer. With…

FAQ

RISC-V MC CPU IP Core: Does RISC-V AHBL bus support burst transaction?

Configuration of the RISC-V MC CPU caches is static based. Lattice currently do not support dynamic configuration of cachesLattice cache related API is limited to flushing instruction cache and invalidating data cache.The RISC-V MC perform burst reads to fill its cache lines when cache…

IP Core

RISC-V AHB-L I/O Physical Memory Protection (IOPMP) IP Core

Lattice Semiconductor’s RISC-V AHB-L IOPMP IP is a standalone memory protection unit that prevents illegal or unexpected access to specific memory regions.

FAQ

Propel: How to perform Memory Allocation in RISC-V

Description:Malloc (Memory Allocation) require you to allocate memory to heap.In Propel SDK, the default heap allocation is 0. You should allocate a minimum amount of memory (example: 0x100) for malloc initialization.Solution:You may find the HEAP_SIZE setting in linker.ld file under your Software…

Demo

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.

Document

Lattice Propel Helps Designers Create Processor-Based Systems in Minutes

Using Propel, designers can quickly and easily generate soft RISC-V-based processor systems to be implemented in the programmable fabric of CrossLink-NX, Certus-NX, and Mach-NX FPGAs, thereby providing sophisticated video processing, system control, and system security capabilities with…