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IP Core

1Gb Ethernet PCS

Archived IP Core supporting ORCA FPGAs - For reference only

IP Core

2.5Gbps Ethernet PCS IP Core

The adaptable Lattice 2.5Gbps Ethernet PCS IP Core offers a physical coding sublayer for Ethernet ports with a 2.5Gbps maximum data throughput.

Document

Gigabit Ethernet PCS IP core

User Manual PDF 395.2KB

Webpage

Programming Cables for PCs

Use to quickly download your design to a Lattice programmable device, or perform various debug operations. Connects a PC to a target board or device via USB or Parallel ports.

IP Core

10Gb Ethernet PCS

Archived IP Core supporting ORCA FPGAs - For reference only.

Blog

Making PCs Smarter with FPGAs

Low power Lattice FPGAs can enable new AI-powered laptops that improve productivity, security, battery life, and enable compelling new form factors.

IP Core

SGMII and Gb Ethernet PCS IP Core

The archived IP has been merged with the Tri-Speed Ethernet IP Core.

FAQ

For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

The answer depends both on device family and data rate:In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP.In the case of the LatticeECP2M and LatticeECP3 devices, the use of the  hard PCS CTC depends on the mode of operation:You cannot use the…

IP Core

10Gb Ethernet PCS IP Core

The archived IP has been merged with the 10G Ethernet (MAC + PHY) IP Core.

FAQ

PCS Simulation: Iteration Limit Error

Description:An iteration limit error may appear when simulating using the PCS IP core.Solution:There are several possible causes for the Iteration Limit Errors. The polarities of the PCS resets are incorrect. When the SERDES Quad reset is removed, an iteration limit error occurs.…

Reference Design

10 Gb Ethernet MAC & PCS Reference Design

10Gb Ethernet MAC & PCS Reference Design on CertusPro-NX with data generator and checker.

Blog

How FPGAs Enable AI and ML in PCs

FAQ

Can I bypass the FPGA Bridge FIFO in the LatticeECP2/M PCS block?

The LatticeECP2/M FPGA Bridge FIFO is enabled by default in the IPExpress GUI. If the user wants to bypass the FIFO it can be done by editing the auto-config file(.txt) as:ch#_tx_gear_bypass "1" ch#_rx_gear_bypass "1" Where "#" represents the channel number. The entry is case-insensitive.

FAQ

What conditions can lead to a loss of multi-channel alignment on the XAUI PCS IP?

The loss of multi-channel alignment (MCA) in the XAUI PCS IP can be caused by two types of factors:Any condition that can cause a burst of invalid 8b10b characters to the PCS/SERDES QUAD : disturbing the SERDES inputs by physically breaking the linestopping the reference clock to the…

Document

1GbE PCS User Guide

User Manual PDF 143.2KB

IP Core

PHY Interface for PCI Express - PIPE

A standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications

Webpage

Lattice User Presence Awareness Kit

The User Awareness Kit demonstrates the ability to wake and put PCs into sleep modes based on AI accelerated computer vision algorithm running on low power Lattice FPGA.

FAQ

All Devices:  Do Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518 bytes as specified in IEEE 802.3ae? 

There is no limitation on the Ethernet frame size as far as the Lattice XAUI PCS cores (LatticeSC flexiPCS Core and XAUI PCS IP Core for LatticeECP2M) are concerned. The XAUI PCS cores will allow transmission and reception of any frame size, including jumbo frames.…

FAQ

LatticeECP3: Why does the SGMII and Gb Ethernet PCS IP reduce the Inter Packet Gap between Ethernet frames?

Description:The Inter Packet Gap (IPG) shrink (deleting of /I2/ ordered set) will always happens as long as there is a PPM (Part per Million) difference between the local reference clock and the remote reference clock, and the remote reference clock is faster than the local reference clock .…

FAQ

LatticeECP3:  Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?

The LatticeECP3 2.5 GBE MAC and PCS IPs described in IPUG98 and IPUG99, will run at 1.25 Gbps by changing the ref_clk clock source to 125 Mhz as shown in the "PHY with Host Bus Control Interface" figure of  IPUG99. The byte_clk and word_clk will be 125 MHZ and 62.5 MHZ respectively, as one…