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IP Core

1Gb Ethernet PCS

Archived IP Core supporting ORCA FPGAs - For reference only

IP Core

2.5Gbps Ethernet PCS IP Core

The adaptable Lattice 2.5Gbps Ethernet PCS IP Core offers a physical coding sublayer for Ethernet ports with a 2.5Gbps maximum data throughput.

Webpage

Programming Cables for PCs

Use to quickly download your design to a Lattice programmable device, or perform various debug operations. Connects a PC to a target board or device via USB or Parallel ports.

IP Core

10Gb Ethernet PCS

Archived IP Core supporting ORCA FPGAs - For reference only.

Blog

Making PCs Smarter with FPGAs

Low power Lattice FPGAs can enable new AI-powered laptops that improve productivity, security, battery life, and enable compelling new form factors.

FAQ

For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

The answer depends both on device family and data rate:In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP.In the case of the LatticeECP2M and LatticeECP3 devices, the use of the  hard PCS CTC depends on the mode of operation:You cannot use the…

IP Core

SGMII and Gb Ethernet PCS IP Core

The archived IP has been merged with the Tri-Speed Ethernet IP Core.

IP Core

10Gb Ethernet PCS IP Core

The archived IP has been merged with the 10G Ethernet (MAC + PHY) IP Core.

FAQ

PCS Simulation: Iteration Limit Error

Description:An iteration limit error may appear when simulating using the PCS IP core.Solution:There are several possible causes for the Iteration Limit Errors. The polarities of the PCS resets are incorrect. When the SERDES Quad reset is removed, an iteration limit error occurs.…

Reference Design

10 Gb Ethernet MAC & PCS Reference Design

10Gb Ethernet MAC & PCS Reference Design on CertusPro-NX with data generator and checker.

Blog

How FPGAs Enable AI and ML in PCs

FAQ

Can I bypass the FPGA Bridge FIFO in the LatticeECP2/M PCS block?

The LatticeECP2/M FPGA Bridge FIFO is enabled by default in the IPExpress GUI. If the user wants to bypass the FIFO it can be done by editing the auto-config file(.txt) as:ch#_tx_gear_bypass "1" ch#_rx_gear_bypass "1" Where "#" represents the channel number. The entry is case-insensitive.

FAQ

What conditions can lead to a loss of multi-channel alignment on the XAUI PCS IP?

The loss of multi-channel alignment (MCA) in the XAUI PCS IP can be caused by two types of factors:Any condition that can cause a burst of invalid 8b10b characters to the PCS/SERDES QUAD : disturbing the SERDES inputs by physically breaking the linestopping the reference clock to the…

Document

1GbE PCS User Guide

User Manual PDF 143.2KB

IP Core

PHY Interface for PCI Express - PIPE

A standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications

FAQ

What is the clock frequency of the rx_full_clk_ch# from the SERDES PCS when there is no valid data being received?

The rx_full_clk_ch# output from the SERDES PCS maintains its relationship to the SERDES reference clock (refclk) so long as the Clock and Data Recovery (CDR) circuit maintains a lock condition. Without valid data arriving the CDR is not guaranteed to stay locked. The rx_full_clk_ch# output is…

FAQ

Is there a signal or indicator in the LatticeSC/M flexiPCS, that can be used to know if the XAUI PCS has completed configuration and is ready for passing traffic?

The LatticeSC/M flexiPCS XAUI layer does not have a specific signal to indicate that all XAUI functions are complete. However , assuming that the RX SERDES is receiving IDLE data (AKR) patterns, then the two major PCS functions that need to be completed before sending functional…

FAQ

Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?

Lattice Diamond: ECP2M: PCS: Yes, you can control where an LatticeECP2M (Physical Coding Sublayer) PCS block is located. The PCS blocks on an LatticeECP2M device can be located at either the upper right, upper left, lower right or lower left. These regions are called…

FAQ

LatticeSC/M: What effect does a PCS local/remote fault signal to the 10Gb+ Ethernet MAC have on the MAC TX and RX logic?

Description:The XAUI PCS communicates the local/remote link fault to the MAC via the XGMII RX data/control bus during the IDLE period, as defined by the IEEE specification. No other signals are used to communicate fault signaling.When the RX MAC receives a fault sequence, the fault sequence…

FAQ

All Devices:  Do Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518 bytes as specified in IEEE 802.3ae? 

There is no limitation on the Ethernet frame size as far as the Lattice XAUI PCS cores (LatticeSC flexiPCS Core and XAUI PCS IP Core for LatticeECP2M) are concerned. The XAUI PCS cores will allow transmission and reception of any frame size, including jumbo frames.…