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TL448K6D-VR System in Package for SteamVR Tracking

Contains all of the necessary processing power to create a SteamVR Tracked device in a 10mm by 16.32mm footprint.

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Lattice Announces New 32 QFN Package For MachXO2 Programmable Logic Devices

Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of its low cost, low power MachXO2™ family of programmable logic devices (PLD) in a new 32 QFN (Quad Flatpack No-leads) package.

FAQ

How to determine lead free package option for Lattice FPGA device?

Please refer to Environmental Information section for RoHS related information.https://www.latticesemi.com/en/Support/QualityAndReliabilityFor lead free part numbers refer to the ordering section of the datasheet but typically the "N" denotes lead free. For example, a lead free T100 would be TN100.

FAQ

MachXO5 : What is the Thermal Resistance Specification for MachXO5 devices caBGA/BBG package

MachXO5 devices base package is based on caBGA and BBG is the variation. Per stated in Part Number Description, Lattice support both BBG256/400 packages.User should follow BBG package Thermal Resistance Specification for MachXO5 devices.Example:LFMXO5-25-7-BBG256I is stated as…

FAQ

Lattice Diamond: Does Diamond timing analysis account for package flight time?

The timing data are measured on the IP boundary; that is, for pin-to-pin delays, that is the timing from the input port of the IP to the output port of the IP. This takes into account the load that the IP sees based on its connections. In the case of IO, there is an assumed 5 pF load (for NX devices…

FAQ

Where can I find a package view of my device?

You can find the mechanical package drawing in our Packaging Diagrams datasheet: https://www.latticesemi.com/view_document?document_id=213 The package view with the pins in your design from the Lattice Diamond Project Navigator's main menu choose: Tools -> Package viewRight…

FAQ

MachXO3/MachXO2:How to monitor INITN in case the current package do not pin-out initn?

In packages such as QFN32 where initn do not have a pin-out, to ensure that initn goes high, we suggest to use tINITL and tDPPINIT to make sure the time that INITN will be high. See image below for datasheet information and sample waveform illustration:

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Lattice ECP5 Family Adoption Grows as New Member Delivers Unprecedented Performance in the Smallest Package

Over 100 early access customers already in progress with Lattice Diamond design tool, development boards, soft IP and reference designs

FAQ

How to find the weight of any device, e.g Pb free 1152 fpBGA package Au wire ?

This data is available in our Device Material Content. Check the below Link Device Material ContentFor example, the Pb free 1152 fpBGA package Au wire weight is 5.50 grams.

FAQ

All Devices: How much weight can the Lattice lead free BGA package tolerate (for heat sink mounting)?

Assuming the pressure on the package is uniform and evenly distributed over the entire topside surface, the loading will be on the BGA ball.  Each lead free ball can withstand ~3N of force (roughly .3 kg) before permanent deformation.Assuming a 484 pin package, the weight can be…

FAQ

What is the difference between QFN32 described in the package diagrams document (FPGA\u2010DS\u201002053) found on pages 18 and 19?

The Option 2 package is for the XO2-256, while the Option 3 package (SG32C) is for the XO2-1200 device.

FAQ

Lattice Diamond Programmer: Are there any differences in Flash programming algorithm of MT25QL512 if we change the package type in Diamond Programmer?

The quick answer is that there are no differences. Assuming you have Diamond 3.11 installed, you may check this default location "C:\lscc\diamond\3.11_x64\data\vmdata\database\flash". This is where the actual flash algorithms used by the programmer are located. From the file "ispVM_008.xdf", if we…

FAQ

Lattice Diamond: How to view die pad to package pins delay numbers using Diamond?

Create or open a Diamond project that has the desired device targeted. Any design works.Open SSV (Spreadsheet View)From the GUI Menu, select File > Export > Pin Layout File..The Column Setting option box opens. Select "Trace Length" which if off by default.Provide a file name and .csv extension.…

FAQ

Crosslink-NX: What is the Max Line Rate of Crosslink-NX Soft Dphy for each package for -7 Speed Grade?

Description:LIFCL17 72 WLCSP: N/A LIFCL17 72 QFN: 861 Mbps LIFCL17 121 CSFBGA: 1034 Mbps LIFCL17 256 CABGA: 1034 Mbps LIFCL40 72 QFN: 861 Mbps   LIFCL40 121 CSFBGA: 1034 Mbps LIFCL40 256 CABGA: 1034 Mbps  LIFCL40 289 CSBGA: 1034 Mbps  LIFCL40 400 CABGA: 1034 Mbps 

FAQ

LatticeECP3: Does Lattice have a demo package integrating the CPRI core with an Ethernet MAC, HDLC framer and processor core?

Description:No. The current Lattice CPRI IP core demo has the C&M channels connection ports which can be connected to an HDLC framer and Ethernet MAC core. The demo has its own test pattern generator and checker, but it does not include the HDLC framer or Ethernet MAC core. Lattice provides Ethernet…

FAQ

ispPAC-POWR1014/A: Where can I find information about the package thermal resistance of the ispPAC-POWR1014/A device?

Solution:The Lattice Thermal Management document provides these details and can be found here: Thermal Management Pg. 3 gives the package data for the TQFP 48, 1.4mm thick (applicable package for the POWR1014/A) for Package Thermal Resistance Junction to Case and Junction to…

FAQ

All Devices: Where can I find the Package Thermal Resistance value of a legacy device or a device that is not specified on the Thermal Management Technical Note (FPGA-TN-02044)?

If not specified on the "Device/Package Thermal Resistance" section you can refer to the generic table, Table 3.1. Package Thermal Resistance. This section specifies the generic thermal resistance for legacy Generic Array Logic (GAL), CPLD, FPGA and Expanded Programmable Logic Device…

FAQ

[CrossLink-NX & MIPI CSI-2/ DSI D-PHY]:What are the Max line Rate (Mbps) of Soft Dphy for Each Package for -9 Speed Grade?

Definition:LIFCL17 72 WLCSP: N/A (No -9 Speed Grade) LIFCL17 72 QFN: 1250 Mbps LIFCL17 121 CSFBGA: 1500 Mbps LIFCL17 256 CABGA: 1500 Mbps LIFCL40 72 QFN: 1250 Mbps LIFCL40 121 CSFBGA: 1500 Mbps LIFCL40 256 CABGA: 1500 Mbps LIFCL40 289 CSBGA: 1500 Mbps LIFCL40 400 CABGA: 1500 Mbps

FAQ

[Crosslink-NX & MIPI CSI2/DSI- DPHY]: What is the Max Line Rate of Crosslink-NX Soft Dphy for each package for -8 Speed Grade?

Definition:LIFCL17 72 WLCSP: 1250 MbpsLIFCL17 72 QFN: 1000 Mbps LIFCL17 121 CSFBGA: 1200 Mbps LIFCL17 256 CABGA: 1200 Mbps LIFCL40 72 QFN: 1000 Mbps  LIFCL40 121 CSFBGA: 1200 Mbps LIFCL40 256 CABGA: 1200 Mbps LIFCL40 289 CSBGA: 1200 Mbps LIFCL40 400 CABGA: 1200 Mbps

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LatticeECP3

LatticeECP3 was designed to offer an efficient FPGA with the benefits of SERDES. Need PCIe, HDMI, CPRI, JESD204, GbE or XAUI? No problem. When performance requirements are high, and size, weight or power is constrained, LatticeECP3 is perfect.