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  • MachXO2

    Webpage

    MachXO2

    MachXO2 FPGA device for quickly implementing system control functions for routers, base stations, servers, storage, industrial and medical applications.
  • MachXO2 Breakout Board

    Board

    MachXO2 Breakout Board

    A simple low-cost board that provides complete I/O access to the MachXO2 plus LEDs, Prototyping Area Power and Programming on-board.
  • MachXO2 Control Development Kit

    Board

    MachXO2 Control Development Kit

    No longer available - for reference only. A full featured MachXO2 development platform for system control + Up to two 7:1 LVDS sources and one output + 128Mbit.
  • MachXO2 Pico Development Kit

    Board

    MachXO2 Pico Development Kit

    Low-cost development platform for MachXO2 (1200ZE) + Battery or USB power; USB I/O and programming + 4-Character LCD...
  • MachXO2 I2C Embedded Programming Access Firmware

    Reference Design

    MachXO2 I2C Embedded Programming Access Firmware

    Provides C code for interfacing to MachXO2 from a microcontroller, and RTL for implementing I2C between an external master and the MachXO2
  • Part Number Reference - MachXO2 Family

    Webpage

    Part Number Reference - MachXO2 Family

    Get the part number description/reference guide for the MachXO2 family here.
  • MachXO2 Dual Sensor Interface Board

    Board

    MachXO2 Dual Sensor Interface Board

    No longer available - for reference only. For use with the LatticeECP3 HDR-60 Video Camera Development Kit and NanoVesta Headboards+For 3D.
  • Do MachXO2 devices support LatticeMico8/LatticeMico32 Soft-Processor?

    FAQ

    Do MachXO2 devices support LatticeMico8/LatticeMico32 Soft-Processor?

    LatticeMicoSystem\u200B: LatticeMico8/LatticeMico32 Soft-processor is not supported for MachXO's family devices.
  • What is the function of the MachXO2 FPGA

    FAQ

    What is the function of the MachXO2 FPGA's Edge Clock Bridge?

    The MachXO2 family, in 1200 LUT and higher densities, have an Edge Clock Bridge that is used to route clock sources onto the Edge Clocks resources in the device. The bridge allows either a primary clock input, or a PLL clock to be routed to the Edge Clock routing on the top and bottom of the…
  • MachXO2:Which IBIS models should I use for the MachXO2 JTAG signal pins?

    FAQ

    MachXO2:Which IBIS models should I use for the MachXO2 JTAG signal pins?

    Solution:For the JTAG input pins, use the LVCMOS input models with bank 0 VCCIO and select the model that has:TCK: bus keeper = NONE TDI: bus keeper = pull up TMS: bus keeper = pull upFor the JTAG output pin (TDO), use LVCMOS output type, bank 0 VCCIO is the VCCJ value, with slow slew setting and…
  • MachXO2: What is best practice for the MachXO2 Slave SPI Chip Select (SN)?

    FAQ

    MachXO2: What is best practice for the MachXO2 Slave SPI Chip Select (SN)?

    The Slave SPI (SSPI) Chip Select (SN) input signal is recommended to be pulled high using an external pull-up resistor.The SSPI configuration port is the second highest in boot priority, with JTAG being the highest priority. Assertion of the SN input, deliberate or not, can cause the MachXO2…
  • What is the behavior of the MachXO2 oscillator when transitioning between configuration and user mode?

    FAQ

    What is the behavior of the MachXO2 oscillator when transitioning between configuration and user mode?

    Although there is only one central clcok oscillator in the MachXO2, the circuit design allows the oscillator to be shared between configuration and user mode without concern to the user design.In MachXO2, there are independent dividers used by the oscillator for the selected user clock…
  • Lattice MachXO2: How to connect the

    FAQ

    Lattice MachXO2: How to connect the 'No Connect' NC pins of MachXO2 packages?

    Description:The 'No Connect' (NC) pins of the MachXO2 packages are true NC, they are unbonded internally, the package pins/balls are floating, therefore the NC pins can be either left floating, connect to GND or VCC.However, care must be taken on a device with NC if future pin migration is…
  • MachXO3: What is the configuration phase time in the start-up phase of MachXO2 and MachXO3 Devices?

    FAQ

    MachXO3: What is the configuration phase time in the start-up phase of MachXO2 and MachXO3 Devices?

    For older devices like MachXO2 and MachXO3, we don't have configuration phase time characterization in the start-up phase. The Product Engineering will characterize the future Devices
  • Lattice Diamond: Is the USE EDGE preference available in the tool for MachXO2 devices?

    FAQ

    Lattice Diamond: Is the USE EDGE preference available in the tool for MachXO2 devices?

    Solution:The USE EDGE preference is not available for MachXO2 devices in Lattice Diamond software. The only way to support the edge is through the design - ECLKSYNC and DDR modules only.
  • How do MachXO2 dual-function output pins behave during configuration mode?

    FAQ

    How do MachXO2 dual-function output pins behave during configuration mode?

    The MachXO2 device family supports dual function pins to provide more general purpose IOs for applications that require high pin counts. The sysConfig and JTAG pins of the device are all dual function pins for the MachXO2 family. These pins can be used as dedicated configuration /…
  • MachXO2: Can the MachXO2 device support PCI-compliant signaling on any GPIO?

    FAQ

    MachXO2: Can the MachXO2 device support PCI-compliant signaling on any GPIO?

    Yes.  However, there are considerations to keep in mind when choosing pins.  The MachXO2 implements two aspects of PCI buffers independently: PCI-level compliant inputs/outputsPCI complaint internal clamps. MachXO2 implements PCI-level compliant inputs/outputs on all the IO (All…
  • MachXO2/MachXO3 :Are there any power supply sequence requirement for MachXO2 and MachXO3 devices?

    FAQ

    MachXO2/MachXO3 :Are there any power supply sequence requirement for MachXO2 and MachXO3 devices?

    POR is controlled by VCC and VCCIO0. As such, these banks should be brought up first. The typical I/O behavior during power-up is described below:The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 reach VPORUP level. This is defined in the Power-On-Reset Voltage table in the…
  • MACHXO2:  What

    FAQ

    MACHXO2:  What's the difference between the TraceID and the USERCODE for MACHXO2 device?

    TraceID is a new feature in MachXO2 devices. It provides a unique 64-bit ID cose for each silicon while using the same design pattern. This is different from the traditional USERCODE which is the same for each design pattern.  For more information on using the TraceID in the MachXO2,…
  • MachXO2: I want to use the output of one Lattice MachXO2 I/O bank to control power on the board to the remaining VCCIO banks. Is this possible assuming that I will first power up the MachXO2 using only the VCC core and one VCCIO bank?

    FAQ

    MachXO2: I want to use the output of one Lattice MachXO2 I/O bank to control power on the board to the remaining VCCIO banks. Is this possible assuming that I will first power up the

    The user can power up the Lattice MachXO2 part using only the VCC core and one VCCIO bank. There are, however, a few constraints:As per the "Typical I/O Behavior During Power-up" section of the MachXO2 Family Data Sheet, the user needs to pick VCCIO0 as the one I/O bank to initially…
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