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ispLEVER v2.0 Service Pack 6 Release Notes

Release Notes PDF 234.1KB

Reference Design

JTAG Embedded Programming using RPi Reference Design

Demo connects Raspberry Pi GPIO pins to JTAG source code in Lattice Radiant™ and Diamond™ software for embedded development and hardware testing.

FAQ

Are there two JTAG ports in the Platform Manager?

Yes, there are two JTAG ports available on the Platform Manager device: Power JTAGFPGA JTAG The Power JTAG interface is used to program the power section of the Platform Manager and the FPGA JTAG is used to configure the FPGA portion of the device.The FPGA…

FAQ

How to resolve the JTAG read/write access issue with Lattice's FPGA that uses JTAG voltage other than 3.3 V?

Description:Device Constraint Editor Global Bank VCCIO setting for Bank0 & Bank1 "CONFIGIO_VOLTAGE_BANK0/CONFIGIO_VOLTAGE_BANK0" is set to "Auto" by default and the voltage is 3.3V.Solution:To workaround on this, user need to assign the correct voltage in…

FAQ

Lattice Diamond Programmer: Do JTAG Full VME embedded source files are supporting JTAG Daisy Chain Programming?

The answer is yes, JTAG Full VME embedded source files are supporting the JTAG Daisy Chain Programming. The chain of devices setup should be done in the Lattice Diamond Programmer file (.xcf) by adding target device/s.

FAQ

What type of pull ups are required for JTAG signals?

User may refer to respective device Hardware Checklist for sysCONFIG port pins pull up requirements.Example: MachXO3D hardware checklist

FAQ

How to use Reveal with Soft JTAG for debugging the design?

See the following example from the CrossLink/LIFMD device family, which does not provide a hard JTAG block. Therefore, Reveal JTAG support is implemented using Soft JTAG debugger logic and GPIO pins will be used for four JTAG pins (JTAG_TCK, JTAG_TDI,…

FAQ

CertusPro-NX: Is it possible to implement JTAG Soft lock/unlock in CertusPro-NX?

There is an available sample design for this implementation but it is not publicly available due to security reasons. The customer should request the design by submitting a technical support ticket.

FAQ

Why are there two JTAG interfaces in the Platform Manager?

There are two JTAG ports integrated into the Platform Manager device: Power JTAG and FPGA JTAG. The Power JTAG interface is used to program the power section of the Platform Manager and the FPGA JTAG is used to con-figure the FPGA portion of the device. The FPGA…

FAQ

Is PROGRAMN pin independent of JTAG programming operations?

The PROGRAMN pin does not affect the JTAG state machine or boundary scan cells. However, the PROGRAMN pin does clear the SRAM configuration memory of the device. Because of this, a logic low signal on PROGRAMN pin at any time during JTAG configuration process may result in a failure…

FAQ

ispVM: Which device is the number 1 device in the JTAG chain in ispVM?

Description:Three identical Lattice devices are in the JTAG chain but each needs different JEDEC pattern. The ispVM GUI shows index number 1, 2, and 3. It is hard for users to match the index number shown in the ispVM to the physical location of the device in the chain.Solution:The device…

FAQ

MachXO2:Which IBIS models should I use for the MachXO2 JTAG signal pins?

Solution:For the JTAG input pins, use the LVCMOS input models with bank 0 VCCIO and select the model that has:TCK: bus keeper = NONE TDI: bus keeper = pull up TMS: bus keeper = pull upFor the JTAG output pin (TDO), use LVCMOS output type, bank 0 VCCIO is the VCCJ value, with slow slew…

FAQ

Can user use FT2232HQ CHANNEL B JTAG CONFIGUARATION for configuration purpose?

FT2332 Channel B is not usable for configuration. It is used for UART and I2C.

FAQ

ispLEVER Classic/Diamond Reveal Analyzer: using a JTAG chain with multiple devices

Reveal Logic Analyzer can be used for On-Chip Debug even if the targeted device is a JTAG chain with multiple devices. Use ispVM to define the JTAG chain and the position of the targeted device in the chain. Then, save the chain (.xcf) file and upload the .xcf file into the Reveal…

FAQ

How do I set the JTAG programming port speed in ispVM System?

One cannot precisely set the JTAG speed in ispVM. The port speed depends on many factors, including the PC speed and the type of cable used (parallel port, USB or USB2).  We run as fast as we can. Though we have no control over the exact speed, ispVM System provides an option to slow the TCK…

FAQ

Why don't ORCAstra modules generated by IPExpress contain JTAG I/O ports?

The ORCAstra module created by IPExpress was updated in ispLever 7.1 SP1. ORCAstra has been updated to permit it to operate in conjunction with other Lattice IP that is accessed using the JTAG port. The most common IP being LatticeMico32 and Reveal.The JTAG I/O ports are no longer…

FAQ

MachXO:Which IBIS models should I use for the MachXO JTAG signal pins?

Solution:For the JTAG input pins, use the LVCMOS input models, input threshold voltage is referenced using the VCCAUX value, and select the model that has: TCK: bus keeper = NONE TDI: bus keeper = pull up TMS: bus keeper = pull up For the JTAG output pin TDO, use LVCMOS output type,…

FAQ

MachXO2: Do the JTAG pins support hysteresis when JTAG_PORT is set to ENABLE?

The Hysteresis for JTAG input pins will be small by default. This can't be changed when the JTAG pins are enabled.

FAQ

Should I connect all the JTAG signals on the download cable to my board?

When using the USB or parallel ispDOWNLOAD cables, connect the "flywire" signals:VCC, TDO, TDI, TMS, GND, and TCK. ispEN (Enable Pin) and ispTRST (Reset Pin) are required for some older devices.Reference the datasheet of a specific device to determine if these two pins are required.Optional signals,…

IP Core

Joint Test Action Group (JTAG) Bridge IP Core

The Lattice Semiconductor JTAG Bridge IP provides an efficient solution for debugging on-board issues by allowing you to access memory and peripheral registers directly using this IP, without involving the processor.