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iCE40 Technology Library

Key Documents, User Manual FPGA-TN-02026 3.3 PDF 2.7MB

Board

iCE40 UltraPlus MDP

Support Discontinued - For Reference Only

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iCE40 UltraPlus

Programmable solution that combines flexible I/O, a configurable architecture, and low power operation in a small form factor. Offering high performance “best-in-class” co-processor capable of highly parallel computing while simultaneously adding high levels of connectivity and support for a wide…

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iCE40 LP/HX

With iCE40 LP/HX FPGAs you can create ingenious mobile products while staying within your cost, power, size and schedule targets. These devices allow you to rapidly customize solutions with off-the-shelf chips. This means maximum product differentiation with minimum cost and effort.

Board

iCE40 Ultra Breakout Board

A simple, low-cost board with rich IO access for evaluation and development with the iCE40 Ultra FPGA.

Board

iCE40 UltraLite Breakout Board

A simple, low-cost board for evaluation and development with the iCE40 UltraLite FPGA. Includes high-power RGB LED.

Board

iCE40 UltraPlus Breakout Board

General purpose board for evaluation and development with iCE40 UltraPlus. Includes access to all IO, high-current LED, switches, etc.

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iCE40 Ultra / Ultra Lite

The iCE40 Ultra / UltraLite, the world’s most integrated mobility focused FPGA, brings you unsurpassed integration at breakneck development speed. It allows customers to upgrade current products or create completely new capabilities, while reducing power, cost, BOM, and size.

FAQ

iCE40 LP/HX: Are the NC (NOT CONNECTED) pins on iCE40 devices internally connected?

The NC (NOT CONNECTED) pins of iCE40 devices are not connected internally.

FAQ

iCE40 LP: Is daisy-chain programming possible on multiple iCE40 chips?

iCE40 does not support daisy chain programming. However, since programming is through SPI interface, SPI_SO, SPI_SI, SPI_SCK, and CRESET_B pins can still be connected on the same bus. SPI_SS pins should be separated which are controlled by the SPI_Master. In using the HW-USB-2B programming cable…

FAQ

iCE40 LP/HX: Does iCE40 LP384 support SB_WARMBOOT device configuration primitive?

SB_WARMBOOT is supported for all iCE40 Devices except for the iCE40-LP384.

FAQ

iCE40 Family: What is the recommended Configuration Mode for NVCM in iCE40 devices?

Description:It is reported that Fast Boot Mode encounters issue when configuring the device in some cases. Solution:The users should implement a Low or Medium Frequency Boot Mode for iCE40 Devices as this provides a more reliable configuration setup.

FAQ

iCE40 UltraPlus: How utilize Differential Input pairs on an iCE40 device?

For iCEcube2 compatible devices (LP/HX/LM/Ultra/UltraLite/UltraPlus), the user needs to use the SB_IO primitive and override the IO_STANDARD parameter to SB_LVDS_INPUT as shown in the rudimentary example below:SB_IO SB_IO_inst ( .PACKAGE_PIN(DATA_IN), .LATCH_INPUT_VALUE(), .CLOCK_ENABLE(),…

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Part Number Reference - iCE40 Family

Get the part number description/reference guide for the iCE40 family here.

IP Core

iCE40 UltraPlus I2S IP

Customize and control an I2S bus - Transmit/Receive from 16 to 32 bits.

Board

iCE40 Ultra Wearable Development Platform

Peripheral and sensor-rich development platform with iCE 40 Ultra and MachXO2 in a wearable watch form factor.

Board

iCE40 Ultra Mobile Development Platform

Support Discontinued - For Reference Only

Webpage

Part Number Reference - iCE40 Ultra / UltraLite /UltraPlus Family

Get the part number description/reference guide for the iCE40 Ultra / UltraLite /UltraPlus family here.

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Industry Accolades Continue for Lattice iCE40 FPGA Family

Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that its ultra-low density iCE40™ FPGA family has been named an Elektra Awards Finalist as “Digital Semiconductor Product of the Year.”

FAQ

iCE40 : What is the default status of I/O pins before the configuration of an iCE40 device?

The default status of I/O pins before the configuration of an iCE40 device is tri-stated with a weak pull-up to VCCIO.