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  • LatticeECP3: In a design that uses generic 8b10B protocol, Is there any example design that uses 16-bit word alignment?

    FAQ

    LatticeECP3: In a design that uses generic 8b10B protocol, Is there any example design that uses 16-bit word alignment?

    Lattice does not have an example 16-bit word alignment code. It is recommended to use the PCS module in IPexpress within the Lattice Diamond software tools to generate the 16-bit word alignment verilog code. Information about the PCS module and options can be found through the online help in the…
  • LatticeECP3, LatticeECP2: What

    FAQ

    LatticeECP3, LatticeECP2: What's the best, first step to debug  looped-back 16-bit data with 8b10b encoding for SERDES/PCS applications?

    For this type of SERDES application, the 8-bit comma character will always occur in the same 8-bit word location in the 16-bit RX data, as long as the transmitter never sends back-to-back commas or sends commas that are an odd number of cycles apart. If the 16-bit boundary is identical to the TX…
  • GbE PCS:Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

    FAQ

    GbE PCS:Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

    Definition:The GbE Link State Machine (LSM) inside the RX side of the PCS monitors the incoming data for COMMA characters. The first time it detects a COMMA character , it assigns an "even" index to the cycle, and expects any new COMMA characters to also appear on an even boundary. If another COMMA…
  • Upon a CDR Loss of Lock event on the LatticeSC/M flexiPCS in 8b10b mode, do I need to monitor both mca_aligned* and lsm_status* to issue an rx_rst?

    FAQ

    Upon a CDR Loss of Lock event on the LatticeSC/M flexiPCS in 8b10b mode, do I need to monitor both mca_aligned* and lsm_status* to issue an rx_rst?

    Please look at section "Lane Resynchronization Upon Loss of CDR Lock" of TN1145.The section explains how it is not required to monitor the mca_aligned signal to issue an rx_rst. Only lsm_status* needs to be monitored.The section also includes state and timing diagrams of the relationship of rx_rst…
  • With the LatticeSC/M flexiPCS in generic 8b10b mode, why do some far end loopbacks not work when I connect the SERDES HDIN* to a Smartbits 1 GbE data generator?

    FAQ

    With the LatticeSC/M flexiPCS in generic 8b10b mode, why do some far end loopbacks not work when I connect the SERDES HDIN* to a Smartbits 1 GbE data generator?

    As mentioned in DS1005, (flexiPCS Testing section): SERDES parallel far-end loopback will not work unless the incoming HDIN data was created by a clock that is fully synchronous to the local SERDES/PCS reference clock (0 ppm). This means the Smartbits and flexiPCS PCS reference clocks must be…
  • Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

    FAQ

    Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

    When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data.During the time the RX clocks are unstable, the pointers on the PCS  RX FPGA  interface FIFO (RX FIFO) can reach invalid values.When the CDR finally locks , you…
  • CertusPro-NX Versa Evaluation Board Mixed Mode PCIe and 8B10B Protocol Demonstration - User Guide

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  • CertusPro-NX Versa Evaluation Board Mixed Mode PCIe and 8B10B Protocol Demo for Windows - Source Code

    Document

  • CertusPro-NX Versa Evaluation Board Mixed Mode PCIe and 8B10B Protocol Demo for Linux - Source Code

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