JESD204B IP Core

Enabling connectivity in HetNet systems

JEDEC Standard No. 204B (JESD204B) describes a serialized interface between data converters and logic devices. It contains the information necessary to allow designers to implement logic devices which can communicate with other devices (converters) that are compliant with the standard. Lattice’s JESD204B 3G/5G IP Core offerings support both an Rx core (ADC to FPGA direction) and/or a Tx core (FPGA to DAC direction). The Rx and Tx cores can each be generated separately and with different parameters.


  • Subsets of JEDEC Standard No. 204B(JESD204B.01) July 2011
  • Rx core performs lane alignment based on Subclass 0 and Subclass 1
  • Rx core performs frame alignment detection / monitoring and octet reconstruction
  • Rx core performs user-enabled descrambling
  • Rx core recovers link configuration parameters during initial lane synchronization and compares them to user selected parameters to generate a configuration mismatch error
  • Tx core performs user-enabled scrambling
  • Tx core generates initial lane alignment sequence
  • Tx core performs alignment character generation
  • Tx core sources link configuration data with user selected parameter values during initial lane synchronization Sequence
  • 16 bit(3G) or 32 bit(5G) fabric interface per channel for low core frequency
  • One-shot frame/multi-frame boundary flags with one clock ahead of data make users easy to control the transition of the state machines for framer / de-framer

Block Diagram

Performance and Size

JESD204B 3G IP Core Quick Facts
FPGA Families Supported LatticeECP3 ECP5
Targeted Device LFE3-70EA-6FN672C LFE5UM-85F-8BG756C
Max Data Rate 3 Gbps 3 Gbps
Data Path Width 16 bits per lane,
32 bits total for 2 lanes
16 bits per lane,
32 bits total for 2 lanes
LUTs Rx:4886/Tx:651 Rx:2276/Tx:534
sysMEM™ EBRs Rx:2/Tx:0 Rx:2/Tx:0
Registers Rx:2174/Tx:266 Rx:2170/Tx:266
JESD204B 5G IP Core Quick Facts
FPGA Families Supported ECP5-5G
Targeted Device LFE5UM5G-85F-8BG756C
Max Data Rate 5 Gbps
Data Path Width 32 bits per lane,
64 bits total for 2 lanes
LUTs Rx:3475/Tx:936
sysMEM™ EBRs Rx:0/Tx:0
Registers Rx:3977/Tx:621

Ordering Information

Family Part Number

IP Version: 3.3

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Quick Reference
JESD204B IP Core User Guide
FPGA-IPUG-02010 2.3 6/20/2017 PDF 3 MB