DDR3 SDRAM Controller

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules compliant with JESD79-3, DDR3 SDRAM Standard, and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to directly deal with the DDR3 memory interface.

DDR3 SDRAM Controller IP Core Pinout Generation Utility

The DDR3 Pinout Generation Utility is a GUI tool capable of generating the pinout and preference files that contain information for a design that uses the DDR3 SDRAM Controller IP core. More information about this utility, including downloads and documentation is available here.

Features

  • Support for all LatticeECP3 “EA” devices
  • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
  • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
  • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
  • Supports x4, x8, and x16 device configurations
  • Support for unbuffered DDR3 DIMM and DDR3 RDIMM module
  • Supports up to one DIMM and two ranks per DIMM
  • Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
  • Programmable CAS latency
  • Programmable CAS Write Latency
  • Read burst type of nibble sequential or interleave
  • Supports automatic DDR3 SDRAM initialization and refresh
  • Automatic Write Leveling for each DQS for DIMM applications. Option to switch of write leveling for On-board memory applications.
  • Supports Power Down Mode
  • Supports Dynamic On-Die Termination (ODT) controls
  • Termination Data Strobe (TDQS) for x8 widths only
  • LatticeECP3 I/O primitives manage read skews (Read Leveling equivalent)
  • Automatic Programmable Interval Refresh or User Initiated Refresh
  • Option for controlling memory reset outside the controller

The DDR3 SDRAM Controller is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Block Diagram

Performance and Size

ECP51
Parameters SLICEs LUTs Registers I/O2 fMAX (MHz)3
Data Bus Width: 8 (x8) 1700 2450 1700 152 400 MHz (800 Mbps)
Data Bus Width: 16 (x8) 1800 2500 1900 230 400 MHz (800 Mbps)
Data Bus Width: 24 (x8) 1800 2560 1900 308 400 MHz (800 Mbps)
Data Bus Width: 32 (x8) 1900 2650 2050 182 400 MHz (800 Mbps)
Data Bus Width: 40 (x8) 2000 2750 2200 192 400 MHz (800 Mbps)
Data Bus Width: 48 (x8) 2100 2800 2350 202 400 MHz (800 Mbps)
Data Bus Width: 56 (x8) 2200 2900 2500 212 400 MHz (800 Mbps)

1. Performance and utilization data are generated targeting an LFE5U/LFE5UM-85F-8MG756 device using Lattice Diamond 3.2 design software with an LFE5U/LFE5UM control pack. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
2. Numbers shown in the I/O column represent the number of primary I/Os at the DDR3 memory interface. User interface (local side) I/Os are not included.
3. The DDR3 IP core can operate at 400 MHz (800 DDR3) in the fastest speed-grade (-8) when the data width is 56 bits or less and one chip select is used.

LatticeECP31, 2,3
Parameters SLICEs LUTs Registers I/O fMAX (MHz)
Data Bus Width: 8 (x8) 1635 2368 1670 42 400 MHz (800 Mbps)
Data Bus Width: 16 (x8) 1810 2505 1960 53 400 MHz (800 Mbps)
Data Bus Width: 24 (x8) 1989 2641 2267 64 400 MHz (800 Mbps)
Data Bus Width: 32 (x8) 2093 2640 2536 75 400 MHz (800 Mbps)
Data Bus Width: 40 (x8) 2058 2671 2377 86 400 MHz (800 Mbps)
Data Bus Width: 48 (x8) 2156 2734 2562 97 400 MHz (800 Mbps)
Data Bus Width: 56 (x8) 2297 2865 2725 108 400 MHz (800 Mbps)
Data Bus Width: 64 (x8) 2389 2978 2901 119 400 MHz (800 Mbps)
Data Bus Width: 72 (x8) 2527 3122 3000 130 333 MHz (666 Mbps)

1. Performance and utilization data are generated targeting an LFE3-150EA-8FN1156C device using Lattice Diamond 1.4 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
2. EA silicon support only.
3. The DDR3 IP core can operate at 400 MHz (800 DDR3) in the fastest speed-grade (-8, -8L, or -9) when the data width is 64 bits or less and one chip select is used.

Ordering Information

Family Part Number
ECP5 Contact Lattice Sales
LatticeECP3 (EA) DDR3-P-E3-U1

IP Version: 1.4.

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference Information Resources Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Double Data Rate (DDR3) SDRAM Controller IP Core User's Guide
IPUG80 1.9 10/10/2016 PDF 4.7 MB
LatticeECP3 DDR3 Demo for the LatticeECP3 I/O Protocol Board User's Guide
UG38 01.4 6/8/2012 PDF 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Implementing DDR3 Memory Controller (LatticeECP3)
1.0 3/10/2010 PDF 147.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP3 DDR3 Demo
1.4 6/8/2012 ZIP 235.3 KB