Lattice Diamond Design Software

Lattice Diamond Software

FPGA Design, Meet Easy.

Exploring Design Alternatives Made Easy – Finding the best solutions for smaller devices often requires evaluating multiple solutions. Lattice Diamond allows easy exploration of alternate solutions without resorting to workarounds.

Easy to Use in Many Ways – Adapting to a new tool is hard. Lattice Diamond makes this easier by adapting to your style of working and by providing tools that make common tasks easier. No matter how you like to work, Lattice Diamond can adapt to your style.

Design Flow Tailored for Lattice Devices – Applications that use low-density and ultra low-density FPGAs require flexibility, verification, and the ability to iterate quickly. Lattice Diamond does this and more.

Features

  • Complete GUI based FPGA design and verification environment
  • Design exploration in a single project with multiple implementations and settings strategies
  • Graphical environment for managing and navigating timing and power results

Getting Started

  1. Download Software Below - Windows / Linux
  2. Install: follow the installation guide, found in Documents section below.
  3. License: determine which license type you need, then request it on our licensing page via the button below.

Jump To

Diamond Base Downloads

Windows OSWindows

The Diamond Base executable contains all of the design tools and features for you to use Lattice FPGAs from design entry to bitstream download. The supported Windows Operating Systems are Windows XP, Windows Vista (32-bit), Windows 7 (32-bit or 64-bit), and Windows 8 (32-bit or 64-bit).

Package Operating System Version Date Format Size
Lattice Diamond Windows 32-bit 3.3 10/6/2014 ZIP 1.5 GB
Lattice Diamond Windows 64-bit 3.3 10/6/2014 ZIP 1.5 GB

Linux OS Linux

The Diamond Base executable contains all of the design tools and features for you to use Lattice FPGAs from design entry to bitstream download. The supported Linux Operating Systems are Red Hat Enterprise Linux version 4.X, 5.X, 6.X, or Novell SUSE Linux Enterprise 10 SP1 or 11 operating system.

Package Operating System Version Date Format Size
Lattice Diamond Linux 32-bit 3.3 10/6/2014 RPM 1.1 GB
Lattice Diamond Linux 64-bit 3.3 10/6/2014 RPM 1.2 GB

Software Downloads & Documentation

Quick Reference Technical Resources Information Resources Downloads
  TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeMico Embedded Function Block 3.2 6/27/2014 PDF 417.6 KB
LatticeMico Fault Logger 3.1 2/26/2014 PDF 177.6 KB
LatticeMico GPIO 3.1 2/19/2014 PDF 312.9 KB
LatticeMico PMBus 3.3 10/6/2014 PDF 657.7 KB
LatticeMico SDRAM 3.1 2/26/2014 PDF 964.8 KB
LatticeMico SPI Flash 3.1 2/26/2014 PDF 243.9 KB
LatticeMico VID 3.2 3.2 6/27/2014 PDF 203.2 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Jitter Analysis in Lattice Diamond TN1241 1.1 9/20/2011 PDF 1.4 MB
LatticeMico32 Migration Concerns Post ispLEVER 8.1 and Diamond 1.0 TN1221 11/5/2010 PDF 404.1 KB
Using Lattice Diamond Pin Layout Files and Pinout Files AN8087 1.0 7/18/2011 PDF 160.2 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond Installation Guide for Linux 3.3 10/6/2014 PDF 460.1 KB
Diamond Installation Guide for Windows 3.3 10/6/2014 PDF 699.4 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Clarity User Guide 3.3 3.3 10/6/2014 PDF 518.1 KB
Design Planning 3.1 2/26/2014 PDF 1.8 MB
Diamond 3.3 User Guide 3.3 10/6/2014 PDF 4 MB
FPGA Libraries Reference Guide 3.3 3.3 10/6/2014 PDF 2.3 MB
HDL Coding Guidelines 2.1 2/21/2013 PDF 209.2 KB
LatticeMico32 HW User Guide 3.2 6/27/2014 PDF 1.4 MB
LatticeMico32 SW Developer User Guide 3.2 6/27/2014 PDF 5 MB
LatticeMico8 Developer User Guide 3.2 6/27/2014 PDF 3.2 MB
PAC-Designer Software User Manual 6.28 6.28 6/27/2014 PDF 3.3 MB
Platform Designer 3.3 User Guide 3.3 10/6/2014 PDF 659.2 KB
Programming Tools User Guide 3.2 3.2 6/27/2014 PDF 4.6 MB
Reveal 3.1 Troubleshooting Guide 3.1 2/26/2014 PDF 138.7 KB
Reveal 3.3 User Guide 3.3 10/6/2014 PDF 668.9 KB
Timing Closure 3.1 2/26/2014 PDF 1.1 MB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond 3.3 Known Issues 3.3 10/6/2014 PDF 436.1 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
PCN10A-11 Notification of Intent to Freeze ispLEVER After Version 8.2 PCN10A-11 1.0 7/25/2011 PDF 52.7 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Diamond Software Product Brief I0207 3.0 1/8/2014 PDF 2.2 MB
Lattice Diamond Software Product Brief (Chinese Language Version) I0207CG 3.0 1/8/2014 PDF 1.4 MB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond 3.3 Release Notes 3.3 10/6/2014 PDF 137.5 KB
LatticeMico System for Diamond 3.3 Release Notes 3.3 10/6/2014 PDF 133 KB
Software Cable Support 2.0 7/16/2012 PDF 194.8 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Diamond Tutorial 3.2 6/27/2014 PDF 2.3 MB
Lattice Synthesis Engine Tutorial 3.1 3.1 2/26/2014 PDF 244.3 KB
LatticeMico32 Tutorial for Diamond 3.2 6/27/2014 PDF 8.1 MB
LatticeMico8 Tutorial 3.1 2/26/2014 PDF 5.5 MB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond 3.3 32-bit Encryption Pack for Linux 3.3 10/6/2014 714 KB
Diamond 3.3 32-bit Encryption Pack for Windows 3.3 10/6/2014 2.9 MB
Diamond 3.3 32-bit for Linux 3.3 10/6/2014 RPM 1.1 GB
Diamond 3.3 32-bit for Windows 3.3 10/6/2014 ZIP 1.5 GB
Diamond 3.3 64-bit Encryption Pack for Linux 3.3 10/6/2014 720 KB
Diamond 3.3 64-bit Encryption Pack for Windows 3.3 10/6/2014 2.9 MB
Diamond 3.3 64-bit for Linux 3.3 10/6/2014 RPM 1.2 GB
Diamond 3.3 64-bit for Windows 3.3 10/6/2014 ZIP 1.5 GB
LatticeMico System for Diamond 3.3 32-bit Linux 3.3 10/6/2014 RPM 341.8 MB
LatticeMico System for Diamond 3.3 64-bit Linux 3.3 10/6/2014 RPM 345.7 MB
LatticeMico System for Diamond 3.3 Windows 3.3 10/6/2014 ZIP 391.7 MB
Linux Installers MD5 Checksums 3.3 3.3 10/6/2014 TGZ 0.8 KB
ORCAstra Standalone 3.3 for Windows 3.3 10/6/2014 ZIP 34.2 MB
PAC Designer 6.29 for Windows 6.29 10/6/2014 ZIP 120.2 MB
Power Estimator 3.3 32-bit for Linux 3.3 10/6/2014 RPM 238.1 MB
Power Estimator 3.3 32-bit for Windows 3.3 10/6/2014 ZIP 230 MB
Power Estimator 3.3 64-bit for Linux 3.3 10/6/2014 RPM 240.7 MB
Power Estimator 3.3 64-bit for Windows 3.3 10/6/2014 ZIP 241.5 MB
Programmer Standalone 3.3 32-bit for Linux 3.3 10/6/2014 RPM 52.5 MB
Programmer Standalone 3.3 32-bit for Windows 3.3 10/6/2014 ZIP 52.6 MB
Programmer Standalone 3.3 64-bit for Linux 3.3 10/6/2014 RPM 53.5 MB
Programmer Standalone 3.3 64-bit for Windows 3.3 10/6/2014 ZIP 56.8 MB
Programmer Standalone Encryption Pack 3.3 32-bit for Linux 3.3 10/6/2014 28 KB
Programmer Standalone Encryption Pack 3.3 32-bit for Windows 3.3 10/6/2014 1.9 MB
Programmer Standalone Encryption Pack 3.3 64-bit for Linux 3.3 10/6/2014 29 KB
Programmer Standalone Encryption Pack 3.3 64-bit for Windows 3.3 10/6/2014 1.9 MB
Reveal Standalone 3.3 32-bit for Linux 3.3 10/6/2014 RPM 4.5 MB
Reveal Standalone 3.3 32-bit for Windows 10/6/2014 ZIP 48.2 MB
Reveal Standalone 3.3 64-bit for Linux 3.3 10/6/2014 RPM 45.6 MB
Reveal Standalone 3.3 64-bit for Windows 3.3 10/6/2014 ZIP 52.5 MB

Licensing

Diamond can be used with either a free license or a subscription license.
Read Licensing FAQ

Diamond Software Free License

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. The free license enables users to design and evaluate the performance of non-SERDES based Diamond supported devices.

Request a Free License

Diamond Software Subscription License

Design exploration made easy. The full subscription license enables users to design and optimize solutions for all Diamond supported devices, without resorting to workarounds. Implementations can be executed in parallel on multi-core machines to enable you to find the best solution faster.

Request a Subscription License

Device Support by License
Product Subscription License Free License
ECP5 Check Mark -
LatticeECP3 Check Mark -
LatticeECP2M/S Check Mark -
LatticeECP2S Check Mark -
MachXO3 Check Mark Check Mark
MachXO2 Check Mark Check Mark
LatticeXP2 Check Mark Check Mark
LatticeECP2 Check Mark Check Mark

Diamond Feature List

  • Standard FPGA design flow functions
  • Lattice Synthesis Engine (LSE): Lattice developed logic-synthesis tool designed specifically to produce the best possible results for ultra-low density and low density FPGAs (for more information please click here – go to LSE page)
  • Intuitive HDL text editor that includes keyword highlight support for VHDL, Verilog HDL, EDIF, and Lattice Preference Language
  • IPexpress: an integrated interface to Lattice catalog of functional modules, reference designs, and intellectual property(IP), all optimized for Lattice programmable products
  • Netlist Analyzer: an integrated pre and post synthesis result GUI
  • LSE editor
  • Clarity Designer
  • Platform Designer: a tool that enables you to create and control a complete hardware system using the Platform Manager 2 device or MachXO2 with external analog sense and control (ASC)
  • Lattice Synthesis Engine (LSE): Lattice developed logic-synthesis tool designed specifically to produce the best possible results for ultra-low density and low density FPGAs (for more information please click here – go to LSE page)
  • Spreadsheet View: GUI tool to allow users to enter and view design constraints such as pin assignments, clock resource usage, global preferences, timing preferences and more
  • Package View: Easy graphical assignment tool of signals to pins that also allows SSO noise analysis
  • Floorplan View to provide the ability to view and edit placement constraints
  • Physical View to provide a detailed read-only view of the physical routing of paths for more detailed understanding of timing issues
  • Netlist View to provide browsing of design ports, instances, and nets for drag and dropping into other views such as Package View for setting constraints
  • NCD View to provide access to detailed usage information of physical components such as SLICEs, PIOs, IOLOGIC, and other elements
  • Device View to provide the ability to browse device specific resources and cross-probe to other views
  • Cross probing across the views above
  • ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization without having to use a full editor such as EPIC
  • Multiple implementations in a project to allow multiple versions of a design within a single project for easy design exploration
  • Multiple Strategies for implementation “recipes” to be applied to any implementation within a project or shared between projects
  • Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results
  • Timing Analysis View offers an easy to use graphical environment for navigating timing information
  • Power Calculator uses highly accurate data models along with a data driven power model to provide power estimation and calculation results, graphical power displays, and reports
  • Reveal Inserter uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis
  • Reveal Analyzer features the ability to use, multi-event triggering which can be dynamically changed at run-time and an integrated waveform for displaying captured events from the target FPGA
  • Simulation Wizard to guide you through all the necessary steps to get your design to a simulator in the format you want
  • Fully integrated into Diamond and standalone, Programmer allows easy direct normal programming of single or multiple FPGA devices
  • Diamond Deployment Tool provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method
  • Tcl Scripting Support
  • Third Party Tools: Synopsys Synplify Pro and Aldec Active-HDL Lattice Edition II
  • Click here to see an Overview of all Features and Key Concepts related to Diamond

Version History

Diamond Version 3.3

  • Windows 8 support
  • Lattice Synthesis Engine (LSE) expanded support for the following family of devices:
    • ECP5 devices
  • Controlled support for XO3L devices in csfBGA packages (121, 256, 324 pin). Targeting a design to any of these packages in Diamond 3.3 release has certain risks as these products will change in the future. Contact techsupport for more information and to request access
  • Note that the XO3L csfBGA pinouts are being re-designed. Designing to these packages in Diamond 3.3 has risks as the pinouts will change significantly
  • IPexpress now supports MIPI D-PHY for XO2/XO3L. IPexpress enables user to quickly create transmit or receive MIPI interfaces. These interfaces can either support both high speed and low power lanes, or to reduce IO, support high speed lane only. Pin/Pad reports more clearly show which IOs are for MIPI to support board design. See technote TN1202, TN1203 for more details on implementing MIPI D-PHY on XO2 and TN1280 & TN1281 for XO3L
  • LSE expanded support for Netlist Analyzer, a tool that allows users to view the pre-synthesis (RTL) and post-synthesis version of their design as a schematic. This feature allows users to preview or review their designs when LSE is chosen
  • LSE expanded support for synthesis attributes such as full_case, parallel_case, syn_enum_encoding, and syn_sharing
  • Clarity Designer expanded support for Virtual VCCIO for DDR memory. Virtual VCCIO improves interface speed by lowering SSO effect. When using Clarity Planner to assign DDR memory pins, the Virtual VCCIOs will be automatically placed in the correct locations within each DQS group for ease of use
  • Clarity Builder now supports block connections using schematic tool for connecting design blocks together.
  • Diamond Programmer
    • Support for new FTDI cable (HW-USBN-2B) and the ability to upgrade the cable firmware.
    • Now includes device database version in log file
    • Support for iCE40 Ultra (iCE5LP) devices without license control
  • Deployment Tool
    • Supports SPI Flash read mode for external memory and dual boot options for ECP5
    • Added support for 512Mb SPI Flash
    • Removed ECP5 Quad I/O SPI Flash support for external memory
    • Includes device database in log file
    • Support iCE40 Ultra (iCE5LP) devices without license control
  • The File List can now show Reveal Analyzer files (.rva) in addition to Reveal Inserter files (.rvl) in the Debug Files folder. Each rva file will show which rvl file it is associated with in the list
  • Platform Designer now supports PMBus Adapter component. The PMBus Adapter, while being compatible with PMBus standard 1.2, also supports sophisticated power sequencing as well as PMBus 1.3 features such as automatic voltage scaling, very fast fault detection etc. A PMBus controller can now manage all analog supplies on the board by using standard PMBus commands. Designers can now iterate through power sequencing without modifying the PMBus controller firmware
  • Diamond online help now supported on Chrome Browser
  • Improved Search capabilities for Diamond help
    • New toolbar for simultaneous access to index, content, and search subpages in the same web location. With this capability, the state of the subpages are preserved for ease of reading
    • Search box in the toolbar
    • Search while you type: The list of hits appears and is modified in the search page while user is typing for faster results
    • Search results have context: Each search hit includes the first few lines of the topic to help you decide if the topic is relevant to your question
    • Search results re-organized: Hits from all the books are listed in relevance order, thereby increasing the likelihood that the first few hits are the most relevant
    • Search allows the use of quotation marks can be used for specific strings

Lattice Diamond 3.2

  • Adds support for all ECP5 devices
  • Clarity Designer is a new tool with improved design entry methods to allow creating, connecting, and placing systems (ECP5 support only)
  • Reveal support for ECP5 SERDES debug for hardware debugging assistance
  • Adds support for all MachXO3L devices
  • GDDR x4 support in MachXO3L for implementation of high speed interfaces while running core frequency at slower rate such as MIPI D-PHY and subLVDS.
  • LatticeMico System support in MachXO3L for embedded design development.
  • Adds support for MachXO2 LCMXO2-2000ZE in WLCSP49 package.
  • Lattice Synthesis Engine (LSE) expanded support for the following family of devices:
    • MachXO3L device
    • ECP5 devices (pure HDL designs only)
  • LSE expanded to support Synopsis Design Constraints (SDC) for commonly used timing constraints. This facilitates timing constraint entry for users who preferred to use SDC based timing constraints.
  • LSE expanded to support various Synplify Pro's synthesis attributes. This allows users to migrate existing Synplify Pro based design to LSE with minimal rewriting of attributes.
  • Enhanced the Auto Hold Correction algorithm. With the new algorithm, designs with zero setup timing score are more likely to have their hold violations fixed. Furthermore after hold correction, the setup timing score should remain at zero. This feature helps user by increasing the yield of usable designs.
  • Enhanced handling of HDL attributes and edits in Spreadsheet View. The enhancement follows the rule that constraints entered in LPF override those entered in HDL flow.
  • If Synopsys Design Constraints (SDC) are used for synthesis, they can now be automatically translated to LPF language and used in the MAP/PAR process. The LPF file created to accomplish this is not visible from Diamond but the constraints can be seen from SpreadSheet View (SSV) much like HDL attributes can be seen from SSV. Automatically using SDC in MAP/PAR is the default behavior in new projects, but not in existing projects. This feature is enabled/disabled through the synthesis strategy setting: “Use LPF Created from SDC in Project” (both LSE and Synplify). This feature provides a single entry point for timing constraints and can help manage preferences that must be defined on nets.
  • ECO editor log information persists. This allows users to the the log information after closing and reopening the window.
  • Messaging System Enhancements
  • Diamond Programmer Enhancements
  • Deployment Tool Enhancements
  • Programming File Utility Enhancements
  • Model 300 Utility Enhancements
  • Platform Designer Enhancements
    • Updates to VMON table, IMON table, VID IP, and I2C slave address
    • Additional Hot swap support
  • Synopsys Synplify Pro has been updated to version I-2013.09L-SP1-1
  • Aldec Active-HDL LE II has been updated to version 9.3

Diamond Version History

Click here to see all Diamond Version History.

Videos

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. The videos below include an overview of new features in Diamond along with several key improvements and changes in specific areas from earlier software environments. Click on the video links to download an MP4 file which you can then play in your video player of choice.


Available Videos
Video Title Time Size Abstract
Diamond Overview 14:48 28MB Lattice Diamond software includes many new features. This video overview briefly covers several new features and abilities such as the new user interface, design flow, and several tool views that are available.
Diamond Key Concepts 10:25 21MB Lattice Diamond software includes several new key concepts. This video discusses the structure of Diamond projects and the use of implementations, strategies, and folders within projects. Additionally the video discusses shared design memory use, and context sensitive views.
Diamond Importing from ispLEVER 4:47 10MB Lattice Diamond software uses a different project structure than the previous ispLEVER software. This video describes how to import an ispLEVER project into Diamond.
Diamond Design Flow Changes 8:23 16MB Lattice Diamond software features a similar design flow to previous software with some changes and enhancements. This video describes the design process flow and the use of the Process view, File List view, and Run Manager view.
Diamond Timing Analysis Overview 9:36 21MB Lattice Diamond software includes a new Timing Analyzer View that provides a rich graphical interface to viewing timing constraint paths, reports, and schematics. Additionally, the ability to change timing constraints and directly run a timing analysis without re-implementing the design significantly speeds the timing closure process. This video describes the management of the Timing Analyzer files, the new Timing Analyzer UI, and how to make timing constraint changes and generate new timing results.
Diamond Power Calculator 5:06 13MB Lattice Diamond software includes an improved Power Calculator view. A new feature is the ability to manage power project files (PCF) directly in the File List view. This video describes the management of the Power Calculator files and the behavior of the Power Calculator view.
Diamond Reveal Hardware Debugger 8:09 14MB Lattice Diamond software includes improved Reveal Inserter and Reveal Analyzer views for hardware debugging. The Reveal Analyzer view features a streamlined interface including an updated waveform display featuring multiple cursors and rubber banding for measurements. This video describes the management of the Reveal debug files and the new Reveal Analyzer waveform changes.
Diamond Simulation Flow 6:37 11MB Lattice Diamond software includes changes to projects that support multi-file simulation testbenches and allow different models for simulation or synthesis for a single module. The Simulation Wizard has been enhanced to parse for the simulation top and to pass this information and other options directly to a simulator. This video describes the simulation features provided with the software and their basic usage.
Diamond Tcl Scripting Support 2:41 5MB Lattice Diamond software includes new Tcl dictionaries that provide the ability to script the design flow and several key views. This video describes the available Tcl dictionaries and how to run Tcl commands from the UI or the Tcl console.
Diamond Programmer 4:17 6MB Lattice Diamond software includes Programmer that provides the ability to directly program one or multiple FPGA devices on the same scan chain. This video describes how to use it from the UI or outside of DIamond.