RISC-V MC CPU IP Core: Does RISC-V AHBL bus support burst transaction?
- Configuration of the RISC-V MC CPU caches is static based. Lattice currently do not support dynamic configuration of caches
- Lattice cache related API is limited to flushing instruction cache and invalidating data cache.
- The RISC-V MC perform burst reads to fill its cache lines when cache is enabled. The burst length is equal to one cache line which is eight, 32-bit words.
- The RISC-V MC data cache is write-through thus it is not feasible to initiate burst writes from RISC-V CPU. All writes will be single beat.