Lattice Radiant: What is a possible reason for an LPDDR4 Memory Controller timing violation for Nexus Devices?
The timing issue can be due to the CPU.
The LPDDR4 MC instantiates a small Risc-V CPU which implements the LPDDR4 training routes. This CPU runs on pclk_i which can be at a different frequency with aclk_i.
The maximum frequency for pclk_i, when the device performance grade is 7 is around 80MHz with +/-10 tolerance.