MachXO2: How can shift register delay be optimized?
Often in designs, data path delays are implemented with the shift registers. Long delays require many shift registers, which consume a significant FPGA register resources.
In many cases, using RAM-based shift registers will improve resource utilization. In Lattice FPGA devices, slices can be configured as a distributed RAM. By using Distributed RAM along with control logic to implement the shift registers, register resource usage can be reduced.
For example, a 4-bit data bus and 16-cycle delay typically requires 32 logic slices (64 registers). However, it can be implemented using only 7 slices with a RAM-based shift register. This saves 78% of logic resource in this case.
The Lattice Diamond IPexpress tool is used to quickly and easily generate RAM-based shift registers logic.