The following is an example Verilog code that assigns with a delay of 1 time unit across the instantiation "inst" of myand module:
myand #1 inst(a, b, z);
When user place that code into synthesis, Synplify Pro or Lattice Synthesis Engine thinks that user is passing a parameter as indicated in the error below:
@E: CG624 :"C:\my_project\top.v":9:2:9:5|Too many instance parameter assignments
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 23 15:45:36 2012
###########################################################]
Synthesis exit by 2.
Done: error code 2
Whenever you have a "#<VALUE>" in between module instantiation name and module name, synthesis tools translate this as parameter.
The work around is to place translate_off and translate_on statements around the delay. The following code is an example for the workaround:
myand
/* synthesis translate_off */
#1
/* synthesis translate_on */
inst(a, b, z);