This reference design demonstrates a RISC-V-based host controller that configures the Avant FPGA using the target SPI port in x8 DDR mode. During the target SPI x8 configuration process, the bitstream is first read from an SPI flash device and loaded into DDR memory. It is then transferred byte-by-byte through the host controller general purpose input/output (GPIO) pins to the Avant device target SPI port. Additionally, this reference design includes C source code that demonstrates the complete process of configuring the Avant device through the target SPI port.