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  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • UART Reference Design

    Reference Design

    UART Reference Design

    The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.
    UART Reference Design
  • SDR SDRAM Controller-Advanced Reference Design

    Reference Design

    SDR SDRAM Controller-Advanced Reference Design

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller-Advanced Reference Design
  • SPI Controller - WISHBONE Compatible

    Reference Design

    SPI Controller - WISHBONE Compatible

    Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.
    SPI Controller - WISHBONE Compatible
  • Read and Write Usercode

    Reference Design

    Read and Write Usercode

    Read or change a Usercode or User Electronic Signature (UES) through general I/O without reprogramming the entire on-device Flash or interrupting the system.
    Read and Write Usercode
  • Fast Page Mode DRAM Controller

    Reference Design

    Fast Page Mode DRAM Controller

    Implements a Fast Page Mode (FPM) DRAM Controller
    Fast Page Mode DRAM Controller
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