The Lattice WISHBONE compatible UART (Universal Asynchronous Receiver/Transmitter) peripheral provides an interface between the WISHBONE system bus and an RS232 serial communication channel. This UART reference design contains a receiver and a transmitter. The receiver performs serial-to-parallel conversion on the asynchronous data frame received from the serial data input SIN. The transmitter performs parallel-to serial conversion on the 8-bit data received from the CPU. In order to synchronize the asynchronous serial data and to insure the data integrity, Start, Parity and Stop bits are added to the serial data. In FIFO mode, the RBR (Receiver Buffer Register) in the RXCVER block and the THR (Transmit Hold Register) in the TXMTT block become 16-word-deep FIFOs. In non-FIFO mode, these are simple registers.
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Performance and Size
| Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| LCMXO2-1200HC-4TG144CES | Verilog | >60MHz | 52 | 274 LUTs | 1.3 |
| LCMXO2-1200HC-4TG144CES | VHDL | >60MHz | 52 | 267 LUTs | 1.3 |
| LCMXO2280C-5T144C | Verilog | >60MHz | 52 | 253 LUTs | 1.3 |
| LCMXO2280C-5T144C | VHDL | >60MHz | 52 | 256 LUTs | 1.3 |
| LFXP2-5E-5TN144C | Verilog | >60MHz | 52 | 323 LUTs | 1.3 |
| LFXP2-5E-5TN144C | VHDL | >60MHz | 52 | 312 LUTs | 1.3 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
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