[Blog] Advancing Open, Secure AI Infrastructure at OCP Global Summit 2026BlogEntryPage5a72c214-d67d-4cf3-9ebf-423c47ff5b43Blog/Blog/2026/10/15/07/28/Advancing-Open-Secure-AI-Infrastructure-at-OCP-Global-Summit-2026https://edge.sitecorecloud.io/latticesemi9e32-latticesemi06bb-prod9ecc-d341/media/Project/Lattice/LatticeSemi/Images/SearchThumbnails/blog.png?sc_lang=enAs AI data centers scale, the question for operators is shifting from how fast systems run to whether they can be trusted to run autonomously . That question was at the center of our week at OCP Global Summit 2026 in San Jose. If we missed you at the event, here is a recap of what Lattice and AMI, a Lattice company, brought to the community. Launching SCMP: Bringing Open Standards to Infrastructure Control The headline moment was a joint keynote introducing the Secure Control and Management Plane (SCMP) , a new Open Compute Project workstream. S ystem designers are facing four key challenges when making infrastructure decisions: 1. Accelerated shift left schedules as time-to-market is a competitive advantage, 2. Increasing system complexity associated with AI deployments at scale, 3. Security that spans from components to fleet s, and 4. Future proofing infrastructure to keep up with the rapid pace of innovation. Today, much of how a rack boots, verifies firmware, and recovers from failure is defined separately by each vendor. That makes it hard for operators to build trust across a mixed-vendor system, and harder still to verify it. SCMP aims to change that by defining an open, vendor-neutral way to establish trust from the silicon root of trust up through the rack and pod. This is essential a s we move toward an autonomous future including space data centers . T he testbeds for autonomy are already underway on Earth in the form of humanoids, factory au tomation, power and cooling technologies, and dark data centers . This new workstream i s founded by AMD, AMI , Arm, ASPEED, Intel, Jabil, Lattice, Microsoft, and NXP, covering silicon, firmware, manufacturing, and operations. The workstream is open to every OCP participant, and its work begins in Q4 2026. Introducing Sentry 5.0: Preparing Platform Security for the Quantum Era Alongside SCMP, we announced Lattice Sentry solution stack (v 5 .0) , which adds post-quantum cryptography to platform firmware resilience and attestation. The value is straightforward: firmware is a prime target for attackers, and the cryptography protecting it will need to hold up against future quantum capabilities. Sentry 5.0 lets designers protect and recover firmware today while building on algorithms aligned with CNSA 2.0 and NIST guidance. It also works with AMI Tektagon to cover provisioning through lifecycle management. Demonstrating Secure, Quantum-Ready Infrastructure Demonstrations at our booth showed how Lattice FPGAs act as the control and trust layer across the data center, from the silicon root of trust to the rack. Highlights included: Post-quantum security and root of trust : Lattice Sentry 5.0 authenticated, protected, and recovered BMC and host CPU firmware using PQC-signed images. Other demos showed Lattice Mach -N2 running ML-DSA, ML-KEM, and AES-256-GCM in hardware, SPDM 1.4 attestation with PQC, and a firmware TPM (with SecEdge ) and verified entropy module (with Quside ) on the Lattice MachXO5 -NX . Simpler boot and open management : Lattice FPGAs verify firmware before a server boots and streamline how it is managed. In the SPI-less boot demo, a Lattice FPGA checks the BIOS signature before the processor runs it, which removes the need for local flash. Other demos showed Lattice FPGAs consolidating BMC-to-server management and sideband signals onto a single USB link, and automatically discovering and connecting host platforms, all using OCP and DMTF standards. Rack-scale platforms : Lattice FPGAs provide platform control inside AI hardware. In Delta Networking s 102.4 Tbps liquid-cooled switch, they manage power sequencing and optical module connectivity. In the ASRock Rack server built on the Arm AGI CPU , they add secure management and OCP-standard connectivity alongside the CPU and BMC. AI-enabled sensor aggregation : Lattice s Holoscan sensor bridge solution connects sensors to NVIDIA platforms. With Tauro Technologies, the Holoscan sensor ingest platform uses a low power Lattice CertusPro -NX FPGA to combine multiple camera inputs into one 10 GbE stream for NVIDIA Orin and Thor platforms, with precision time synchronization. Meanwhile, right next door at the AMI booth, demos centered on open, silicon-agnostic firmware and management software. Highlights included Secure firmware and platform root of trust : AMI Tektagon provides a silicon-agnostic platform root of trust, with PQC-ready firmware signing, verification, and recovery aligned to NIST SP 800-193 and the EU Cyber Resilience Act. The current PQC implementation runs on Lattice MachXO5D -NX. OpenPRoT , an open-source project built with industry partners, demonstrated a standards-based BMC firmware update using PLDM Type 5, in which the root of trust verifies every update before it is applied. Open, modular management and firmware development: AMI s MegaRAC OneTree demos showed hardware modules that describe themselves, so one firmware image adapts across DC-MHS platforms. They also showed BMC-to-host management consolidated over a single USB connection (OBMF-ICP), and unified Redfish rack management. AMI also showed a composable firmware framework built on EDK2 and Project Mu, and AMILi A , an AI assistant for firmware development and support. Together, the two booths showed one path from the silicon root of trust to the rack. Looking Ahead Thank you to everyone who stopped by, and to our fellow founding contributors for their commitment to SCMP. The work now moves from announcement to action , and we invite operators, silicon suppliers, ODMs, and system integrators to help shape it. To see demo videos and resources from our OCP Global Summit presence, visit the OCP Summit landing page . To join the workstream, visit the OCP community page or contact us . To learn more about Sentry 5.0, visit the Lattice Sentry webpage . To build quantum-resistant, open platforms for your AI data centers, contact us to see how Lattice can enable your secure infrastructure design .As AI data centers scale, the question for operators is shifting from how fast systems run to whether they can be trusted to run autonomously . That question was at the center of our week at OCP Global Summit 2026 in San Jose. If we missed you at the event, here is a recap of what Lattice and AMI, a Lattice company, brought to the community. Launching SCMP: Bringing Open Standards to Infrastructure Control The headline moment was a joint keynote introducing the Secure Control and Management Plane (SCMP) , a new Open Compute Project workstream. S ystem designers are facing four key challenges when making infrastructure decisions: 1. Accelerated shift left schedules as time-to-market is a competitive advantage, 2. Increasing system complexity associated with AI deployments at scale, 3. Security that spans from components to fleet s, and 4. Future proofing infrastructure to keep up with the rapid pace of innovation. Today, much of how a rack boots, verifies firmware, and recovers from failure is defined separately by each vendor. That makes it hard for operators to build trust across a mixed-vendor system, and harder still to verify it. SCMP aims to change that by defining an open, vendor-neutral way to establish trust from the silicon root of trust up through the rack and pod. This is essential a s we move toward an autonomous future including space data centers . T he testbeds for autonomy are already underway on Earth in the form of humanoids, factory au tomation, power and cooling technologies, and dark data centers . This new workstream i s founded by AMD, AMI , Arm, ASPEED, Intel, Jabil, Lattice, Microsoft, and NXP, covering silicon, firmware, manufacturing, and operations. The workstream is open to every OCP participant, and its work begins in Q4 2026. Introducing Sentry 5.0: Preparing Platform Security for the Quantum Era Alongside SCMP, we announced Lattice Sentry solution stack (v 5 .0) , which adds post-quantum cryptography to platform firmware resilience and attestation. The value is straightforward: firmware is a prime target for attackers, and the cryptography protecting it will need to hold up against future quantum capabilities. Sentry 5.0 lets designers protect and recover firmware today while building on algorithms aligned with CNSA 2.0 and NIST guidance. It also works with AMI Tektagon to cover provisioning through lifecycle management. Demonstrating Secure, Quantum-Ready Infrastructure Demonstrations at our booth showed how Lattice FPGAs act as the control and trust layer across the data center, from the silicon root of trust to the rack. Highlights included: Post-quantum security and root of trust : Lattice Sentry 5.0 authenticated, protected, and recovered BMC and host CPU firmware using PQC-signed images. Other demos showed Lattice Mach -N2 running ML-DSA, ML-KEM, and AES-256-GCM in hardware, SPDM 1.4 attestation with PQC, and a firmware TPM (with SecEdge ) and verified entropy module (with Quside ) on the Lattice MachXO5 -NX . Simpler boot and open management : Lattice FPGAs verify firmware before a server boots and streamline how it is managed. In the SPI-less boot demo, a Lattice FPGA checks the BIOS signature before the processor runs it, which removes the need for local flash. Other demos showed Lattice FPGAs consolidating BMC-to-server management and sideband signals onto a single USB link, and automatically discovering and connecting host platforms, all using OCP and DMTF standards. Rack-scale platforms : Lattice FPGAs provide platform control inside AI hardware. In Delta Networking s 102.4 Tbps liquid-cooled switch, they manage power sequencing and optical module connectivity. In the ASRock Rack server built on the Arm AGI CPU , they add secure management and OCP-standard connectivity alongside the CPU and BMC. AI-enabled sensor aggregation : Lattice s Holoscan sensor bridge solution connects sensors to NVIDIA platforms. With Tauro Technologies, the Holoscan sensor ingest platform uses a low power Lattice CertusPro -NX FPGA to combine multiple camera inputs into one 10 GbE stream for NVIDIA Orin and Thor platforms, with precision time synchronization. Meanwhile, right next door at the AMI booth, demos centered on open, silicon-agnostic firmware and management software. Highlights included Secure firmware and platform root of trust : AMI Tektagon provides a silicon-agnostic platform root of trust, with PQC-ready firmware signing, verification, and recovery aligned to NIST SP 800-193 and the EU Cyber Resilience Act. The current PQC implementation runs on Lattice MachXO5D -NX. OpenPRoT , an open-source project built with industry partners, demonstrated a standards-based BMC firmware update using PLDM Type 5, in which the root of trust verifies every update before it is applied. Open, modular management and firmware development: AMI s MegaRAC OneTree demos showed hardware modules that describe themselves, so one firmware image adapts across DC-MHS platforms. They also showed BMC-to-host management consolidated over a single USB connection (OBMF-ICP), and unified Redfish rack management. AMI also showed a composable firmware framework built on EDK2 and Project Mu, and AMILi A , an AI assistant for firmware development and support. Together, the two booths showed one path from the silicon root of trust to the rack. Looking Ahead Thank you to everyone who stopped by, and to our fellow founding contributors for their commitment to SCMP. The work now moves from announcement to action , and we invite operators, silicon suppliers, ODMs, and system integrators to help shape it. To see demo videos and resources from our OCP Global Summit presence, visit the OCP Summit landing page . To join the workstream, visit the OCP community page or contact us . To learn more about Sentry 5.0, visit the Lattice Sentry webpage . To build quantum-resistant, open platforms for your AI data centers, contact us to see how Lattice can enable your secure infrastructure design .FPGA, post-quantum cryptography, PQC, platform firmware resilience, PFR, Lattice Sentry, CNSA 2.0, AMI Tektagon, SPDM attestation, firmware attestation, disaggregated AI infrastructure2026-10-16T13:00:00Z
[Blog] Advancing Open, Secure AI Infrastructure at OCP Global Summit 2026
Posted 10/16/2026 by Lattice Semiconductor
As AI data centers scale, the question for operators is shifting from how fast systems run to whether they can be trusted to run autonomously. That question was at the center of our week at OCP Global Summit 2026 in San Jose. If we missed you at the event, here is a recap of what Lattice and AMI, a Lattice company, brought to the community.
Launching SCMP: Bringing Open Standards to Infrastructure Control
The headline moment was a joint keynote introducing the Secure Control and Management Plane (SCMP), a new Open Compute Project workstream. System designers are facing four key challenges when making infrastructure decisions: 1. Accelerated shift left schedules as time-to-market is a competitive advantage, 2. Increasing system complexity associated with AI deployments at scale, 3. Security that spans from components to fleets, and 4. Future proofing infrastructure to keep up with the rapid pace of innovation.
Today, much of how a rack boots, verifies firmware, and recovers from failure is defined separately by each vendor. That makes it hard for operators to build trust across a mixed-vendor system, and harder still to verify it. SCMP aims to change that by defining an open, vendor-neutral way to establish trust from the silicon root of trust up through the rack and pod. This is essential as we move toward an autonomous future including space data centers. The testbeds for autonomy are already underway on Earth in the form of humanoids, factory automation, power and cooling technologies, and dark data centers. This new workstream is founded by AMD, AMI, Arm, ASPEED, Intel, Jabil, Lattice, Microsoft, and NXP, covering silicon, firmware, manufacturing, and operations. The workstream is open to every OCP participant, and its work begins in Q4 2026.
Introducing Sentry 5.0: Preparing Platform Security for the Quantum Era
Alongside SCMP, we announced Lattice Sentry™ solution stack (v5.0), which adds post-quantum cryptography to platform firmware resilience and attestation. The value is straightforward: firmware is a prime target for attackers, and the cryptography protecting it will need to hold up against future quantum capabilities.
Sentry 5.0 lets designers protect and recover firmware today while building on algorithms aligned with CNSA 2.0 and NIST guidance. It also works with AMI Tektagon™ to cover provisioning through lifecycle management.
Demonstrating Secure, Quantum-Ready Infrastructure
Demonstrations at our booth showed how Lattice FPGAs act as the control and trust layer across the data center, from the silicon root of trust to the rack.
-
Post-quantum security and root of trust: Lattice Sentry 5.0 authenticated, protected, and recovered BMC and host CPU firmware using PQC-signed images. Other demos showed Lattice Mach™-N2 running ML-DSA, ML-KEM, and AES-256-GCM in hardware, SPDM 1.4 attestation with PQC, and a firmware TPM (with SecEdge) and verified entropy module (with Quside) on the Lattice MachXO5™-NX.
-
Simpler boot and open management: Lattice FPGAs verify firmware before a server boots and streamline how it is managed. In the SPI-less boot demo, a Lattice FPGA checks the BIOS signature before the processor runs it, which removes the need for local flash. Other demos showed Lattice FPGAs consolidating BMC-to-server management and sideband signals onto a single USB link, and automatically discovering and connecting host platforms, all using OCP and DMTF standards.
-
Rack-scale platforms: Lattice FPGAs provide platform control inside AI hardware. In Delta Networking’s 102.4 Tbps liquid-cooled switch, they manage power sequencing and optical module connectivity. In the ASRock Rack server built on the Arm AGI CPU, they add secure management and OCP-standard connectivity alongside the CPU and BMC.
-
AI-enabled sensor aggregation: Lattice’s Holoscan sensor bridge solution connects sensors to NVIDIA platforms. With Tauro Technologies, the Holoscan sensor ingest platform uses a low power Lattice CertusPro™-NX FPGA to combine multiple camera inputs into one 10 GbE stream for NVIDIA Orin and Thor platforms, with precision time synchronization.
Meanwhile, right next door at the AMI booth, demos centered on open, silicon-agnostic firmware and management software. Highlights included
-
Secure firmware and platform root of trust: AMI Tektagon provides a silicon-agnostic platform root of trust, with PQC-ready firmware signing, verification, and recovery aligned to NIST SP 800-193 and the EU Cyber Resilience Act. The current PQC implementation runs on Lattice MachXO5D™-NX. OpenPRoT, an open-source project built with industry partners, demonstrated a standards-based BMC firmware update using PLDM Type 5, in which the root of trust verifies every update before it is applied.
-
Open, modular management and firmware development: AMI’s MegaRAC OneTree™ demos showed hardware modules that describe themselves, so one firmware image adapts across DC-MHS platforms. They also showed BMC-to-host management consolidated over a single USB connection (OBMF-ICP), and unified Redfish rack management. AMI also showed a composable firmware framework built on EDK2 and Project Mu, and AMILiA™, an AI assistant for firmware development and support.
Together, the two booths showed one path from the silicon root of trust to the rack.
Thank you to everyone who stopped by, and to our fellow founding contributors for their commitment to SCMP. The work now moves from announcement to action, and we invite operators, silicon suppliers, ODMs, and system integrators to help shape it.
