This reference design implements a PCI Express to Gigabit Ethernet network interface controller on the Mach-N2 FPGA. It integrates a PCI Express endpoint with a Tri-Speed Ethernet (TSE) MAC and adds the descriptor-based direct memory access engine and control logic between them that make the board function as a network interface card rather than a transparent bridge. The design is targeted at the Mach-Nexus 2 Evaluation Board.
A Linux kernel driver is supplied in source form. Once it is loaded, the operating system treats the board as an ordinary network adapter, and applications send and receive data through standard sockets.
Features
PCIe-to-Gigabit Ethernet Bridging
- Functions as a NIC (Network Interface Card), bridging data transfer between PCIe Gen4x4 and TSE MAC RGMII
- Supports tri-speed Ethernet operation (10/100/1000 Mbps) with dynamic runtime speed switching
- Sustains 1 Gbps line-rate throughput in both directions, with concurrent bidirectional operation supported
- Supports standard and jumbo frames (MTU 1500 / 9000)
- Descriptor-ring DMA engine with independent TX and RX ring managers, moving packet data directly to and from host memory over native PCIe transactions
Display Control
- LED indicators display real-time PCIe link, TSE MAC, and ETH PHY status
- 3-digit 7-segment display shows active Ethernet speed, clock frequency, and link status (including link-up failure and timeout errors)
Debug Capability
- Per-module statistic counters for system-level debug and performance monitoring
- PCIe-based register access across subsystems:
- ETH PHY via MDIO, TSE MAC via APB and other modules via MMIO for configuration and status readback
- Modular, self-describing register map organized into discovery-capable category regions, with an on-die frequency counter providing live RGMII clock measurement
