MachXO5-NX I2C Reference Design

Data Access to MachXO5-NX Internal Flash through User I2C Bus Interface

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Lattice MachXO5-NX™ I2C Reference Design provides the data access to the MachXO5-NX internal flash through the user I2C bus interface.

The MachXO5-NX I2C reference design initiates and connects the MachXO5-NX flash programming through the user I2C interface. The reference design is based on the RISC-V MC SoC project template with addition of I2C Target component and Internal Flash Controller component, and removal of the Oscillator component.

Features

  • Supports I2C commands to program the MachXO5-NX flash
  • Implement Erase, write, and read on the CFG, UFM, and USERDATA partitions
  • Works on Lattice MachXO5-NX-25 Development Board

Block Diagram

MachXO5-NX I2C Reference Design Block DiagramExpand Image

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5-NX I2C Reference Design – User Guide
FPGA-RD-02299 1.0 1/17/2025 PDF 1.4 MB
MachXO5-NX I2C Reference Design – Source Code
1/17/2025 ZIP 20.7 MB

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