MIPI DSI to DisplayPort Reference Design and Demonstration

A MIPI D-PHY Receiver Front-End Configuration up to Four Lanes

The CertusPro™-NX Mobile Industry Processor Interface (MIPI®) Display Serial Interface (DSI) to DisplayPort (DP) bridge design features a MIPI D-PHY receiver front-end configuration up to four lanes. The bridge decodes MIPI video packets and converts the formatted video data stream into a DisplayPort output. The design supports a range of MIPI DSI video packets and offers flexible DisplayPort lane counts (up to four lanes) and link rates (MIPI up to 891 Mbps, DP up to 5.4 Gbps) to accommodate various resolution and bandwidth requirements.

Features

  • The Lattice MIPI CSI/DSI RX IP supports up to four lanes and lane rates up to 891 Mbps, enabling flexible bandwidth configuration. The IP receives, processes, and converts incoming MIPI video payload packets into Unified Video Streaming Interface (UVSI) packets.
  • The Lattice Video Scaler IP performs high-precision scaling operations, supporting resolution upscaling of video content up to 4K through the UVSI.
  • The Lattice DisplayPort IP transmits serial-digital video output with support up to four lanes and lane rates up to 5.4 Gbps through UVSI.

Jump to

Block Diagram

MIPI DSI to DisplayPort Reference Design and Demonstration Block DiagramExpand Image

MIPI DSI to DisplayPort Reference Design Block Diagram

Documentation

Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
MIPI DSI to DisplayPort Reference Design and Demonstration Documentation
To learn more about this product design and to access the complete source code, bitstream and user guide in GitHub, please click here		1/30/2026WEB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.