This reference design demontrates the techniques necessary for generating long duration timeouts. Timeouts of 2, 4 8 or 16 seconds are demonstrated. The code for performing these kind of timer functions is useful when implementing functions such as watchdog timers, or when monitoring a long or complicated sequence of events.
Features
- Sequences/Toggles LEDs using 2, 4, 8, and 16 second duration timers
- Demonstrates detection of events and triggering or ending sequences
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Block Diagram
Performance and Size
| Tested Devices* | FPGA LUTs |
FPGA Slices |
CPLD Macrocells |
CPLD Product Terms | VMONs | I/Os | Timers | HVOUTs | Revision |
|---|---|---|---|---|---|---|---|---|---|
| LPTM10-12107 | 44 | 25 | 18 | - | 5 | - | 4 | - | 1.0 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
Documentation
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