The Scatter Gather Direct Memory Access Controller (SDMAC) IP core provides access to the main memory independent of the processor. It offloads processor intervention. The processor initiates transfer to SGDMAC and receives an interrupt on completion of the transfer by the DMA Engine.
Resource Utilization details are available in the IP Core User Guide.
Features
- Independent MM2S and S2MM data buffer
- MM2S: AXI-MM to AXI-Stream
- S2MM: AXI-Stream to AXI-MM
- AXI4 Protocol compliant
- MM2S/S2MM AXI4-MM Address width support of 32 or 64 bits.
- MM2S/S2MM AXI4-MM Data width support of 32, 64 or 128 bits.
- MM2S/S2MM AXI4-Steam Data width support of 8, 16, 32, 64 or 128 bits.
- Buffer Descriptor AXI4-MM Address and Data width support of 32 bits.
- AXI4-Lite Address and Data width support of 32 bits.
- Max transfer size per descriptor support of 2^16 Bytes.
- Any-to-any AXI-MM and AXI-S Data Width streaming.
- Configurable MM2S/S2MM local FIFO Depth support of 512, 1024, 2048 or 4096.
