LPDDR SDRAM Controller


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IP ExpressThe LPDDR Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard LPDDR memory devices/modules compliant with JESD209B, LPDDR SDRAM Standard, and provides a generic command interface to user applications. This IP core reduces the effort required to integrate the LPDDR memory controller with the remainder of the application and minimizes the need to directly deal with the LPDDR memory interface.

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    Block Diagram

    LPDDR SDRAM ControllerExpand Image

    Performance and Size

    Parameters SLICEs LUTs Registers fMAX (MHz)
    Data Width: 16
    Row Width: 14
    Col Width: 10
    Wishbone: Disabled    		 900 1675 1100 133
    Data Width: 16
    Row Width: 13
    Col Width: 10
    Wishbone: Disabled    		 850 1600 1000 133
    Data Width: 8
    Row Width: 13
    Col Width: 9
    Wishbone: Disabled    		 850 1575 950 133
    Data Width: 8
    Row Width: 12
    Col Width: 9
    Wishbone: Disabled    		 825 1550 925 133
    Data Width: 16
    Row Width: 14
    Col Width: 10
    Wishbone: Two Ports    		 1200 2300 1500 100
    Data Width: 8
    Row Width: 12
    Col Width: 9
    Wishbone: One Port    		 700 1350 900 100

    1. Performance and utilization data are generated using a LCMXO2-7000HE-6FG484C device in Lattice Diamond 3.1 design software. Performance may vary when using this IP core in a different density, speed or grade within the MachXO2 family.

    Ordering Information

      Part Number
    Device Family Multi-site Perpetual Single Seat Annual
    MachXO2 LPDDRCT-WB-M2-UT LPDDRCT-WB-M2-US

    IP Version: 2.0.

    Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible.

    Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

    Documentation

    Quick Reference
    TITLENUMBERVERSIONDATEFORMATSIZE
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    LPDDR SDRAM Controller IP Core User's Guide
    		IPUG921.32/1/2014PDF2.6 MB

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