Industry standard interface - The Serial Peripheral Interface (SPI) bus provides an industry standard interface between processors and other devices.
Compatible with all SPI Modes - SPI interface is a good choice for designs that require full-duplex capability for sending and receiving data at the same time. The SPI Master Controller can communicate with multiple off-chip SPI ports and can also be configured to support all modes of CPOL and CPHA (00, 01, 10, and 11).
Features
- Implements the Generic Soft SPI Master Controller Reference Design by performing simple transactions to the external SPI Flash device found in the MachXO3-9400 Development Board
- Can also be programmed into a wide array of Lattice FPGAs such as MachXO2™, MachXO3, LatticeECP3™, ECP5™, CrossLink™, CrossLink™-NX, and iCE40 UltraPlus™
- Provision for easy integration of any processor interface
- Up to five slave select outputs
- Configurable timing features for timing-sensitive slave devices
Support Discontinued - For Reference Only
