MIPI DSI Receive Bridge

DSI Receive Reference Design

 

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Flexible MIPI (Mobile Industry Processor Interface) DSI (Display Serial Interface) Receive Bridge - Allows an AP (Application Processors) to interface to a screen that is not designed for mobile applications.

MIPI DSI RX Diagram

Custom Configuration - Click the start here button below and complete the DSI Rx configuration form. We will send you a HDL (Hardware Description Language) netlist for your specific DSI Rx requirements.

Click here to begin

Alternatively you can download the default design which interfaces to 2 lane RGB 888 mode.


Features

  • Supports up to 4 data lanes
  • HS (High Speed) Mode recevie
  • LP (Low Power) Mode transmit and receive
  • Typical power for 2 data lane bridge running at 700Mbps is 20mW
  • Typical power for 4 data lane bridge running at 700Mbps is 32mW
  • Provides a DCS (Display Command Set) encoder for display controls
  • Supports DSI formats RGB, YCbCr and User Defined
  • Output parallel RGB bus supporting up to 36 bits with clock, Hsync & Vsync

Jump to


Block Diagram


Documentation

Quick Reference Technical Resources Information Resources
  TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI DPHY DSI/CSI-2 Example Schematic 1.0 10/29/2013 PDF 72.6 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
D-PHY Reference Design RD1182 1.5 1/31/2015 ZIP 4.2 MB
DSI Rx Reference Design - Documentation RD1185 1.3 4/1/2014 PDF 2.1 MB
DSI Rx Reference Design - Source Code RD1185 1.4 1/1/2015 ZIP 1.6 MB
MIPI D-PHY Interface IP - Documentation RD1182 1.5 1/31/2015 PDF 3 MB
  TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI Display Serial Interface Solution Product Flyer 12.2 10/22/2013 PDF 1.1 MB