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This interface card is used to connect the LatticeECP2 Advanced Evaluation board to an evaluation module for the TI ADS6000 family. Both the LatticeECP2 Advanced Evaluation board and the Texas Instruments (TI) ADS6000 EVM are available separately. The interface card connects to the high-speed Molex/SPI4.2 connector on the LatticeECP2 Advanced Evaluation Board, and a high-density SAMTEC connector on the TI ADS64xx EVM. The interface uses LVDS I/O.
Product Contents
Each Lattice ECP2 Advanced - TI ADS6000 Interface Card includes the following:
- Lattice ECP2 Advanced - TI ADS6000 Interface Card
- Demo documentation (Note: To ensure you are using the latest version, demo code and source files should be downloaded from this web page)
Important: To use this card you will need both a TI ADS6XXX EVM (available from TI) and a LatticeECP2 Advanced Evaluation Board (available from Lattice). These are described below, and available separately. These boards are NOT included with the Interface Card (LFE2-H-IC-EV).
TI ADS6000 Family and Evaluation Modules
TI offers a generic evaluation module (EVM) for the ADS6000 family. This same base EVM design is available for various members of the ADS6000 family. For general evaluation, Lattice recommends using the ADS6425 EVM. The ADS6425 device is a Quad Channel 12-Bit 125-MSPS ADC. the LatticeECP2/M Reference Design enables quick verification of its performance. The reference design described below is intended for use with the TI ADS6425 EVM.
To learn more about the TI ADS6000 family, and purchase a TI ADS6425 EVM, please visit the TI web site. Click on the link for the ADS6xxx device you want, then scroll down to the "Tools and Software" section to learn more about the evaluation module and/or purchase from the TI on-line store.
LatticeECP2 Advanced Evaluation Board
The LatticeECP2 Advanced Evaluation Board includes a rich variety of on-board functions and connectors to help you evaluate the LatticeECP2 FPGA performance in a variety of application spaces. To learn more about this board, please visit the LatticeECP2 Advanced Evaluation Board web page.
Demonstration Reference Design
This reference design enables the LatticeECP2 FPGA to de-serialize ADC code read from the TI ADS 6000 series EVM using LVDS data and clock signals. The input data is captured by the ECP2 FPGA using the built-in DDR registers and the 2X gearing function. The Frame clock is adjusted as required using the on-board PLL of the ECP2 FPGA. The Demo logic will store the first 1020 data samples into the onboard EBR memory block so they can be read later. The Demo design also incorporates the Lattice Reveal Logic Analyzer (included with the ispLEVER FPGA design software) to allow the user to easily read out data values from the memory.
This demonstration reference design consists of a programming bitstream for the LatticeECP2 FPGA, as well as source files that can be used with the ispLEVER FPGA design software. Click the "design files" link at the left of this page to download the latest copy of the demonstration program, and click the "user manuals" link to download the documentation for it.
The TI ADS6000 EVM boards are available in two different versions. One is capable of a 12-bit analog to digital conversion and the other version is capable of 14-bit analog to digital conversion. This Demo is built for versions which use a 12-bit conversion. The TI ADS board is also available in either 2- or 4-channel versions. This Demo was developed using the 4-channel version of the TI ADS board, though it is also possible to use 2-channel board.
Required Software
- ispLEVER for design, fitting, place & route of Lattice programmable devices. If you don't have a copy of the ispLEVER software, the LatticeECP2-50 FPGA is supported in the downloadable ispLEVER-Starter software. The ispLEVER software includes the Reveal logic analyzer, which is used in the demonstration program.
- ispVM software is used to program the LatticeECP2 FPGA.
Ordering Information
Part Number:
LFE2-H-IC-EV
To purchase these boards, please visit our Online Store.
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